Download cmos transmission gate circuits

CMOS TRANSMISSION GATE CIRCUITS
 OBJECTIVES
a) To understand the operating principle of transmission gate.
b) To determine the on and off resistances of the gate.
c) To understand the mode of use of the transmission gates to obtain an amplifier with a digital adjustment
of the gain and a passive integrator with a digital controlled network of capacitors.
 COMPONENTS AND INSTRUMENTATION
In this experiment you will use the 4066 integrated circuit from Fig.1. that include 4 CMOS transmission
gates. Fig.1 presents the connection diagram of the 4066 integrated circuit. In Fig.2 the internal structure and
the symbol of a transmission gate are presented. The connection diagram for the 741 op-amp can be found in
Voltage Comparators with Operational Amplifier experiment.
VDDVCAVCD D D C C
VDD,VSS: positive and negative supply voltages.
A, A;
B, B; C, C; D, D: input/output and output/input for the
transmission gates: A, B, C, D.
VCA,VCB,VCC,VCD: the control voltages for the 4 transmission gates.
14 13 12 11 10 9 8
1
2
3 4 5 6 7
A A B B VCBVCCVSS
Fig.1. IC 4066- connection diagram
To supply the circuit you need a double dc regulated power supply. Because you apply and measure dc
and ac voltages you need a signal generator, a dual channel oscilloscope and a voltmeter.
VDD
TP
INPUT
INPUT
OUTPUT
OUTPUT
Tn
CONTROL
vCo
-VSS
a)
CONTROL
INPUT
OUTPUT
TG
INPUT
OUTPUT b)
Fig.2.CMOS transmission gate.
a) Internal structure; b) Symbol
1
III. PREPARATION
1.P. CMOS TRANSMISSION GATE (TG)
1.1.P. ON AND OFF STATES
The transmission gates from MMC 4066 integrated circuit (IC) are in on state for high control voltages
and in off state for low control voltages.
A.
 What does the output voltage vO(t) of the transmission gate look like for a sinusoidal input voltage, vI(t)
with 3V amplitude and 1KHz frequency, if the control voltage of the gate is vCo=5V? What if vCo=-5V? The
IC which contains the gate has the supply voltages: VDD=5V; VSS=-5V.
 Does the load resistance connected at the output affect the output voltage? If it is so, in what way and in
what state (on/off state)?
B.
 The IC is supplied with 5V. What does vO(t) look like for vI(t) sinusoidal voltage with 7V amplitude,
vCo=5V?
1.2.P EQUIVALENT RESISTANCES OF THE TRANSMISSION GATE
 Because the transmission gate is not ideal, between the input/output terminals there is an equivalent
resistance greater than 0 in the on state, ron, and less than infinite in the off state, roff .
 How do you determine ron and roff if you know for each state of the gate the input voltage, the output
voltage and the load resistance?
2.P. AMPLIFIER WITH DIGITAL ADJUSTMENT OF THE GAIN
 For the circuit in Fig.3, what is the value of the equivalent resistance, RAB, between the points A and B,
for the next combinations of the voltages that control the states of the two transmission gates?
I
II
III
IV
vCo1
vCo2
5V
-5V
5V
- 5V
5V
5V
-5V
-5V

How does vO(t) look like for each case mentioned above if vI(t) is a sinusoidal voltage with the
200mV amplitude and 1KHz frequency? The relation between vO and vI is:
vO  
R AB
vI
R1
P.3 PASSIVE INTEGRATOR WITH A DIGITAL CONTROLLED NETWORK OF
CAPACITANCES
 For the circuit in Fig.4, what is the equivalent capacitance Ceq between the points A and B for the next
combinations of the voltages that control the transmission gates?
I
II
III
IV
vCo1
vCo2
5V
-5V
5V
-5V
5V
5V
-5V
-5V
2
 What is the time constant for each of these situations?
 What does vO(t) look like if vI(t) is a rectangular voltage between 0 and 5V with 100Hz frequency.
IV. EXPLORATION AND RESULTS
1. CMOS TRANSMISSION GATE
1.1. ON AND OFF STATES
A.
Exploration
 The assembly is supplied with a differential voltage (V DD=5V; VSS =-5V; ground=0V) from a dual dc
regulated voltage supply.
 You choose D gate from the four possible transmission gates denoted A, B, C and D (Fig.6).
 At the input of the gate In/Out you apply the voltage vO(t)=3sin(2π1000t)[V][Hz]
Attention: be sure that the operational output (OUT) is not connected to the load resistance.
 At the output of D gate Out/In you connect the load resistance RL2=1K (J11 closed).
 At the control input of the gate (VcoD) you apply a high level voltage by connecting it to VDD (vCo=5V).
 You simultaneous visualise on the oscilloscope (Y–t mode) the input and output voltages (vi(t) and vo(t)).
 At the control input of the gate you apply a low level voltage by connecting VSS (vCo=-5V).
 You will visualise simultaneous on the oscilloscope (Y–t mode) the input and the output voltages (vI(t)
and vO(t)) .You will repeat the above steps for RL1=100 (J10 closed, J11 open).
Results
 Draw the waveforms for the input and the output voltages for vCo=5V, vCo=-5V and for RL2=1K,
RL2=100.
 For what value of vCo is the gate turned off? What about the value for which the gate is turned on?
 Compare the amplitudes of the output voltage obtained for the two values of the load resistance when the
gate is in on state.
 Solve the previous point, but for the off state.
B.
Exploration
 With the high level control voltage vCo=5V and the load resistance RL=1K, you visualise on the
oscilloscope vI(t) and vO(t).
 You increase the amplitude of vI until vO is distorted.
Results
 For what values of the amplitude of vI is the output voltage distorted?
1.2. EQUIVALENT RESISTANCES OF THE TRANSMISSION GATE
 For the chosen transmission gate you apply at the input a sinusoidal signal with 1KHz frequency and the
amplitude smaller than 5V.
Exploration
A. ron
 vCo=5V; the load resistance RL1=100
 With an ac voltmeter or with the oscilloscope you measure vI and vO.
Results
A. ron
The values of vI and vO and the value of the load resistance

3
Compute ron considering the voltage divider formed by ron and RL1.
Exploration
B. roff
 vCo=-5V; the load resistance RL3=470K (J12 closed, J10 open, J11 open).
 With the oscilloscope measure vi and vo.

Results
B. roff
 The values of vI and vO and the value of the load resistance.
 Compute roff .
2.AMPLIFIER WITH DIGITAL ADJUSTMENT OF THE GAIN
Exploration
Build the circuit shown in Fig.3. The transmission gates used in this circuit are A and B. Disconnect all the
jumpers and connect : J14 with J15, J5 with J6, J8 with J9, the operational output (OUT) to the load
resistance, J11 closed, and J2 closed (to connect R2 with R3).
vCoB
vCoA
A
TGA
TGB
R2
R3
B
R1
3,9k
6k
+
vI
33k
vO
1k
RL
Fig.3. Amplifier with digital controlled gain
 The assembly is supplied with a differential voltage (VDD=5V; VSS=-5V; ground=0V)
 vI=100sin(21000t)[mV][Hz]
 Visualise the output from Vo.
 At the control terminals of the two transmission gates (VcoA and VcoB) you apply the next combinations of
voltages :
I
II
III
vCoA
vCoB
5V
-5V
-5V
5V
5V
-5V
 You visualise on the oscilloscope vO(t) and vI(t) for each case mentioned above.
Results




Draw the waveforms for vI(t) and vO(t), for the three cases mentioned above.
What is the value of the voltage gain for each case; AV=vO/vI
How can you explain the differences between the values of the gain in the three cases?
Why do we say that the circuit has a digital adjustment of the gain?
4
3. PASSIVE INTEGRATOR WITH A DIGITAL CONTROLLED NETWORK OF
CAPACITORS
R
A
3,9K
vCoA
vCoB
TGA
TGB
vI
C1
vO
C2
68nF
2,2nF
B
Fig.4. Intergrator with digitally controlled capacitors network
Exploration.
 Build the circuit shown inFig.4. Disconnect all the jumpers and make new connections: J13 with J14, J3
with J4, J7 with J8 and J1 closed (to short-circuit the R2).
 Visualise the output from VO1.
 The assembly is supplied with a differential voltage (VDD=5V; VSS=-5V; ground=0V)
 vI(t) is a rectangular signal between 0 and 5V, with 100Hz frequency, obtained from the signal generator.
 You will visualise vO(t) and vI(t) for the next combinations of the two voltages which control the
transmission gates:
I
II
III
vCoA
vCoB
5V
5V
-5V
5V
-5V
-5V
Results
 Draw the waveforms for vO(t) and vI(t) for the three cases mentioned above.
 How can you explain the different shape of vo for each of the three cases ?
Advice: Consider the circuit time constant (.3 P)
 Why do we say that the circuit has a digital controlled network of capacitors?
5