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Reg. No:…………………………….
KIGALI INSTITUTE OF SCIENCE AND TECHNOLOGY
INSTITUT DES SCIENCES ET TECHNOLOGIE
Avenue de l'Armée, B.P. 3900 Kigali, Rwanda
INSTITUTE EXAMINATIONS – ACADEMIC YEAR 2013
END OF SEMESTER EXAMINATION: MAIN EXAM
FACULTY
SCIENCE
OF
ENGINEERING
or
FACULTY
OF
COMPUTER ENGINEERING & INFORMATION TECHNOLOGY and
APPLIED PHYSICS
FIRST YEAR CEIT or THIRD YEAR PHYSICS SEMESTER II
CIT 3122 : DIGITAL CIRCUITS or PHY 3324: DIGITAL ELECTRONICS
DATE:
/ /2013
TIME: 2 HOURS
MAXIMUM MARKS = 60
INSTRUCTIONS
1. This paper contains Four (4) questions.
2. Answer One compulsory question section A and two any (2) questions in section B
3. The compulsory question mark is 30 Marks and each question of section B is 15 Marks
4. No written materials allowed.
5. Do not forget to write your Registration Number.
6. Do not write any answers on this question paper.
1
SECTION A: COMPULSORY QUESTION
1. a)Prove the following identities using the laws, rules or theorems of Boolean algebra:
i.
(A + B) (A + C) = A + BC
(3 Marks)
(4 Marks)
ii.
b) What is the largest decimal value that can be represented in binary using two bytes?
(2 Marks)
c) Convert the following numbers: Precision limited to 4 bits in fractional part
i.
ii.
(247.36)8 to an equivalent hexadecimal number
(3A.2F)16 to an equivalent decimal number
(2 Marks)
(2 Marks)
d) What is the basic difference between a full-adder and a half-adder?
Make the full-adder truth table and deduce the expressions of its outputs, then draw
its logic diagram and its logic symbol.
(9 Marks)
e) Give any six advantages of the programmable logic devices (PLDs) compared to fixedfunctions Integrated Circuits.
(3 Marks)
f) The waveforms in figure below are applied to the flip-flop as shown. Determine the Q
output starting in the RESET state. Indicate on each clock pulse the change occurred
on the flip-flop.
(5 Marks)
SECTION B: Choose any two questions.
2 a) Clearly explain the difference between the following logic circuits, draw their block
diagram and give an example for each:
2
A combinational circuit and sequential circuits.
(5 Marks)
b) Use a Karnaugh map to simplify the following expression:
(4 Marks)
c) Draw a 3-bit synchronous binary up counter and its timing diagram knowing that the
counter is implemented with positive edge-triggered flip-flops.
(6 Marks)
3. a) Draw and clearly explain the working of a CMOS NOR gate by using a comparison with the
switches. Deduce the truth table of the gate.
(7 Marks)
b) Which of the following involve analog quantities and which involve digital quantities?
i.
ii.
iii.
iv.
v.
vi.
Electronic voting machine
Temperature of a room
Ordinary electric switch
Current flowing out of an electrical outlet
Sand grains on the beach
Sound picked up by a microphone
c) Implement the logic function
(0.5 Mark )
(0.5 Mark
(0.5 Mark )
(0.5 Mark )
(0.5 Mark )
(0.5 Mark )
using NAND gates only.
(5 Marks)
4. a) What is the advantage of a synchronous counter over an asynchronous counter? Give also
its disadvantage.
(3 Marks)
b) Subtract 230 10 from 185 10 by converting to binary and using 2’s complement
(4 Marks)
c)
Make a truth table, and a Karnaugh map for the expression indicated. Then develop the
minimum sum of products form.
Draw the circuit using AND gate, OR gates and NOT gates before and after simplifying the logic
expression.
(8 Marks)
3
MARKING SCHEME: MAIN EXAM in IInd SEMESTER 2013
SECTION A
1. a) Proof of following identities
i.
(3 Marks)
ii.
(4 Marks)
4
b) Largest decimal value that can be represented in binary using two bytes
2 bytes = 16 bits, the largest binary value will be equivalent to decimal 2 16 – 1 = 65,535
c. i) Convert (247.36)8 to an equivalent hexadecimal number
(2 Marks)
(247.36)8 = (010 100 111. 011 110)2
= (1010 0111. 0111 1000)2
= (A7.78)16
ii) Convert (3A.2F)16 to an equivalent decimal number
(2 Marks)
(3A.2F)16 = 3 x 161 + 10 x160 + 2 x16-1 +15 x 16-2
= 48 +10 + 2/16 + 15/(16)2
= 58 + 0.125 + 0.05859
= (58. 1836)10
d) The basic difference between a full-adder and a half-adder is that the full-adder accepts
two input bits and an input carry coming from lower-order bit but the half-adder performs the
addition of two bits; it accepts two binary digits on its inputs and produces two binary digits on
its outputs: a sum bit and a carry bit. Full-adder = 2 half-adders with their output carries ored.
It accepts two input bits and an input carry and generates a sum output and an output carry.
Full-adder truth table
OUTPUT EXPRESSIONS
Σ  ( A  B)  Cin
5
Cout  AB  ( A  B)Cin
Logic symbol
(9 Marks)
e) Six advantages of the programmable logic devices (PLDs): any 6 of the following
advantages.
i.
ii.
iii.
iv.
v.
vi.
vii.
viii.
Stronger logic function
Higher density, usage of much less board space
Flexible design method, designs can be changed without rewiring or
replacing components.
Higher operation rate
Faster implementation
Lower cost implementation
Having encryption function, when the device is encrypted, it can’t be read
and copied.
Convenience for using i.e. Most of PLDs are programmed again and
again. The design can be modified and upgraded conveniently.
(3 Marks)
6
f) Output Q of the flip-flop
(5 Marks)
SECTION B
2. a) The difference between the logic circuits with example for each:
i.
A combinational circuits and sequential circuits.
A combinational logic circuit is one whose outputs depend only on its current inputs; there are
no storage elements in combinational logic circuit.
Examples: one of the following circuits: encoder, decoder, multiplexer, demultiplexer and
adder.
A sequential logic circuit is one whose outputs depend not only on its current inputs, but also
on its past inputs, there are storage (or memory) elements and feedback in sequential logic
circuit. The outputs have the relationship not only with the inputs, but also with previous state
of the storage elements.
7
BLOCK DIAGRAM OF SEQUENTIAL CIRCUIT
Examples: one of the following circuits: Latch, flip-flop
(5Marks)
b) ) Karnaugh map
(4 Marks)
c) A 3-bit synchronous binary counter
8
J 2  K 2  Q1Q0
When the states of all lower-order flip-flops are 1s, the higher-order JK flip-flop operates in
toggle. J  K  Q Q
2
2
1
0
(6 Marks)
The propagation delay is almost no change.
3. a) CMOS NOR gate : 2 NMOS Q1 and Q2 in parallel & 2 PMOS Q3 and Q4 in series.
If A=B=1, Q1 & Q2 are on i.e. closed switches but Q3 & Q4 are off i.e. open switches
then output C =0.
9
If either A or B = 1, associated N-channel Q1 or Q2 turned on but associated P-channel Q3 or Q4
turned off since either Q3 or Q4 off then output C would be 0
If both A=B=0, Q3 or Q4 would be on i.e. closed switches but Q1 or Q2 off i.e. open switches then
output C would be 1
(7 Marks)
i.
ii.
iii.
iv.
Electronic voting machine: Digital
Temperature of a room : Analog
Ordinary electric switch : Digital
Current flowing out of an electrical outlet: Analog
10
(0.5 Mark )
(0.5 Mark
(0.5 Mark )
(0.5 Mark )
v.
vi.
Sand grains on the beach: Digital
Sound picked up by a microphone: Analog
(0.5 Mark )
(0.5 Mark)
c) Implementation of
using NAND gates only.
(5 Marks)
4. a) In a synchronous counter, the external clock pulse is applied to all of the flip-flop
clock inputs simultaneously, so that the flip-flops are clocked at the same time by a
common clock pulse. The advantage of synchronous counters is the speed that they can
be made to produce any binary sequence of any desired length without the long delays
for propagating the clock pulse. But they have a minor disadvantage: containing more
components which make them more expensive.
(3 Marks)
b)Subtract (230)10 from (185)10 by converting to binary and using 2’s complement
185 ÷ 2 = 92 Remainder = 1
230 ÷ 2 =115
Remainder = 0
92 ÷ 2 = 46
115 ÷ 2 = 57
Remainder = 1
Remainder = 0
11
46 ÷ 2 = 23
Remainder = 0
57 ÷ 2 = 28
Remainder = 1
23 ÷ 2 = 11
Remainder = 1
28 ÷ 2 = 14
Remainder = 0
11 ÷ 2 = 5
Remainder = 1
14 ÷ 2 = 7
Remainder = 0
5÷2=2
Remainder = 1
7÷2=3
Remainder = 1
2÷2=1
Remainder = 0
3÷2=1
Remainder = 1
1÷2=0
Remainder = 1
1÷2=0
Remainder = 1
(185) 10 = (10111001) 2
10111001-11100110
and
(230) 10 = (11100110) 2
is equivalent to 10111001
+00011010
11010011
1’s complement of 11100110 = 00011001
2’s complement = 00011001 + 1 = 00011010
No carry, 1’s complement 00101100
2’s complement 00101101
Answer = - 00101101
(4 Marks)
c)
Circuit using AND gate, OR gates and NOT gates before simplification
12
Truth table
Minimum sum of products form.
Logic circuit after simplification
13
(8 Marks)
14
Reg. No:……………………………
KIGALI INSTITUTE OF SCIENCE AND TECHNOLOGY
INSTITUT DES SCIENCES ET TECHNOLOGIE
Avenue de l'Armée, B.P. 3900 Kigali, Rwanda
INSTITUTE EXAMINATIONS – ACADEMIC YEAR 2013
SUPPLEMENTARY EXAM
FACULTY OF ENGINEERING and FACULTY of SCIENCE
COMPUTER ENGINEERING & INFORMATION TECHNOLOGY
FIRST YEAR CEIT and THIRD YEAR PHYSICS SEMESTER II
CIT 3122 : DIGITAL CIRCUITS and PHY 3324: DIGITAL ELECTRONICS
DATE:
/ /2013
TIME: 2 HOURS
MAXIMUM MARKS = 60
INSTRUCTIONS
1. This paper contains Four (4) questions.
2. Answer One compulsory question section A and two any (2)questions questions in
section B
3. The compulsory question mark is 30 Marks and each question of section B is 15 Marks
4. No written materials allowed.
5. Do not forget to write your Registration Number.
6. Do not write any answers on this question paper.
15
SECTION A: COMPULSORY Question
1. a)Convert the following numbers:
(3A.2F)16 to an equivalent decimal number with 4 digits in the fractional
part
(2 Marks)
(0.577024)8 to an equivalent hexadecimal number
(2 Marks)
i.
ii.
b) What is the largest decimal value that can be represented in BCD code using two
bytes?
(2 Marks)
c) Prove the following Boolean identities using the laws, rules or theorems of Boolean
algebra:
i.
ii.
( A + B)( A + B)( A + C) = A C
A B C + A B C + A B C = A ( B + C)
(4Marks)
(3Marks)
d) Use a Karnaugh map to simplify the following expression:
(5 Marks)
e) What is a half-adder? Make the half-adder truth table and deduce the expressions of
its outputs; draw its logic diagram and logic symbol.
(7 Marks)
f) Briefly explain the classification of counters and give an example for each.
(5 Marks)
SECTION B: Choose any two questions
2. a) What is the simplest multiplexer? Give its logic diagram and the expressions of its
outputs
( 5 Marks)
b) Express the decimal number -39 as an 8-bit number in the sign-magnitude, 1’s
complement, and 2’s complement forms.
(5 Marks)
c) Analyze the circuit given in the figure below. Write down the truth table for the circuit
and use it to determine the output when:
i) A = B = C = 1
ii) A = C = 0 and B = 1
iii) What is the logic function of the circuit?
16
(5 Marks)
3. a) Draw and clearly explain the construction and the working principle of a CMOS
inverter circuit by using a comparison with the switches.
(5 Marks)
b) Implement the following expression as it is below, and then simplify it in SOP form.
(6 Marks)
c) What are the digital technology advantages over analog technology? List any four
advantages.
(4 Marks)
4. a) Draw and clearly explain the working of an Active-LOW input S-R latch, assuming
latch initial state is RESET (0). Give its function truth table and logic symbol
(6 Marks)
b) The waveforms in figure below are applied to the flip-flop as shown. Determine the
Q output, starting in the RESET state. Indicate on each clock pulse the change for the
output Q of the flip-flop.
(4 Marks)
17
c) Briefly explain the following terms:
i.
Registers
ii.
SIPO.
(2 Marks)
(3 Marks)
18
MARKING SCHEME: SUPPLEMENTARY EXAM in IInd SEMESTER 2013
Section A
1. i. (3A.2F)16 = 3 x 161 + 10 x 160 + 2 x 16-1 + 15 x 16-2
= 48 + 10 + (2/16) + (15/16x16)
= (58.1836)10
(2 Marks)
ii. (0.577024)8 in binary 0.101 111 111 000 010 100
In hexadecimal system 0.1011 1111 1000 0101 = (0. BF85)16
(2 Marks)
b) 2 bytes = 16 bits, in BCD code, each decimal digit, 0 through 9, is represented by binary code
of four bits. 16 bits will represent 4 decimal digits and the largest decimal value will be 9999.
(2 Marks)
c) Prove the following Boolean identities:
i.
(4 Marks)
ii)
19
(3 Marks)
d) Karnaugh map
(5 Marks)
e) The half-adder
The half-adder is a combinational circuit that performs the addition of two bits; it accepts
two binary digits on its inputs and produces two binary digits on its outputs: a sum bit and a
carry bit.
The basic rules for binary addition
20
The sum output is a 1 only if the inputs A and B are not the same therefore it can be expressed
as the exclusive-OR of the inputs variables. The output carry is produced with an AND gate with
A and B on the inputs.
Logic diagram
Output expressions
Σ  AB  A B  A  B
Cout  AB
Logic symbol
(7 Marks)
f) The classification of counters with one example for each.
i.
According to the way they are clocked
Synchronous counter when the external clock pulse is applied to all flip-flop clock inputs
simultaneously.
Asynchronous counter (ripple counter) when the external clock pulse is only applied to the first
flip-flop clock input (or few clock inputs of flip-flops).
21
ii.
According to sequence of states
Binary counter with 4-bit or BCD counter
iii.
iv.
According to the number of states (modulus); the modulus of a counter is the number
of unique states that the counter will sequence through. modulus-4,
According to the direction that the counter goes through its sequence
Up counter (000, 001, 010, 011, 100, 101, …) Or Down counter 000, 111, 110, 101, 100, 011
(5 Marks)
…)or Up/Down counter
2. a) The simplest multiplexer is 1-of-2 data selector. It is a digital switch which connects
data from one of 2 sources to its output i.e. from two inputs to a single output. The
data-select input S0 controls which route is chosen.
(5 Marks)
b) The decimal number -39 as an 8-bit number in the sign-magnitude, 1’s
complement, and 2’s complement forms.
39 ÷ 2 = 19
Remainder = 1
19 ÷ 2 = 9
Remainder = 1
9÷2=4
Remainder = 1
4÷2=2
Remainder = 0
2÷2=1
Remainder = 0
22
1÷2=0
Remainder = 1
8-bit number equivalent to + 39 will be 00100111 in the sign-magnitude
8-bit number equivalent to - 39 will be 10100111 in the sign-magnitude
1’s complement form of – 39 = 11011000
2’s complement form of – 39 = 11011000 + 1 = 11011001
(5 Marks)
c)
Truth table for the circuit
i) A = B = C = 1
ii) A = C = 0 and B = 1
iii) The logic function of the circuit is the OR logic function because the output X is at logic 1
whenever any or more of the input is at 1.
(5 Marks)
23
3. a) CMOS inverter circuit




P- channel and N-channel connected in series
Input applied at the 2 gates connected together
2 drains tied together
Output taken at the common drain
Knowing that NMOS is on when Vin is high (1) and off when Vin is low (0) and PMOS is on
when Vin is low (0) and off when Vin is high (1).
1. When Vin is low (0), Q2 is on, i.e. closed switch but Q1 is off, i.e. open switch then the
output will be high (1).
2.
When Vin is high (1), Q1 is on, i.e. closed switch but Q2 is off, i.e. open switch then
the output will be low (0).
24
We can establish the functional behavior of the NMOS Q1 and PMOS Q2.on the following
table
(5 Marks)
b) Implementation of the expression
Simplification in the SOP form
(6 Marks)
25
c) Digital technology advantages over analog technology: any four of the following answers
 Less affected by noise
 Easy information storage
 Easier to design
 Secrecy stronger
 Accuracy and precision easier to maintain
 Operation can be programmed i.e. controlled by a set of stored instructions.
(4 Marks)
4. a ) Active-LOW input S-R latch
Consisting of two cross-coupled NAND gates with two complementary outputs, Q and Q
Q is HIGH (or 1), the latch SET and Q is LOW (or 0), the latch
RESET
Assuming latch initial state is RESET (0)
 S = 1 and R = 1
When S = 1 , R = 1, the latch remain in initial state, there is no change. Both inputs are inactive
26
 S = 0 and R = 1
When S = 0 and R = 1, the latch SET
 S = 1 and R = 0
When S = 1 and R = 0, the latch RESET.
 S = 0 and R = 0
The condition, S = 0 and R = 0 is invalid for active-LOW input SR latch. Output states are
uncertain when input LOWs are released at the same time.
27
(6 Marks)
.b) Output Q of the flip-flop
(4 Marks)
c) Registers are a combination of several flip-flops used for storing groups of bits or for
shifting bits from one position to another within the register or out of the register to
another circuit.
(2 Marks)
SIPO stands for serial in/parallel out, it is a way of shifting data bits in which data bits
entered serially one at a time with least significant bit (LSB) first but data are taken out with
all bits are available simultaneously rather than on a bit-by-bit basis.
(3 Marks)
28