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Diode Logic
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To the left you see a basic Diode Logic OR gate. We'll assume that a logic 1
is represented by +5 volts, and a logic 0 is represented by ground, or zero volts.
In this figure, if both inputs are left unconnected or are both at logic 0, output Z
will also be held at zero volts by the resistor, and will thus be a logic 0 as well.
However, if either input is raised to +5 volts, its diode will become forward
biased and will therefore conduct. This in turn will force the output up to logic
1. If both inputs are logic 1, the output will still be logic 1. Hence, this gate
correctly performs a logical OR function.
To the right is the equivalent AND gate. We use the same logic levels, but
the diodes are reversed and the resistor is set to pull the output voltage up to a
logic 1 state. For this example, +V = +5 volts, although other voltages can just
as easily be used. Now, if both inputs are unconnected or if they are both at
logic 1, output Z will be at logic 1. If either input is grounded (logic 0), that
diode will conduct and will pull the output down to logic 0 as well. Both inputs
must be logic 1 in order for the output to be logic 1, so this circuit performs the
logical AND function.
In both of these gates, we have made the assumption that the diodes do not
introduce any errors or losses into the circuit. This is not really the case; a
silicon diode will experience a forward voltage drop of about 0.65v to 0.7v
while conducting. But we can get around this very nicely by specifying that any
voltage above +3.5 volts shall be logic 1, and any voltage below +1.5 volts
shall be logic 0. It is illegal in this system for an output voltage to be between
+1.5 and +3.5 volts; this is the undefined voltage region.
Individual gates like the two above can be used to advantage in specific
circumstances. However, when DL gates are cascaded, as shown to the left,
some additional problems occur. Here, we have two AND gates, whose outputs
are connected to the inputs of an OR gate. Very simple and apparently
reasonable.
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Diode Logic makes use of the fact that the electronic device known as a
diode will conduct an electrical current in one direction, but not in the other. In
this manner, the diode acts as an electronic switch.
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But wait a minute! If we pull the inputs down to logic 0, sure enough the
output will be held at logic 0. However, if both inputs of either AND gate are at
+5 volts, what will the output voltage be? That diode in the OR gate will
immediately be forward biased, and current will flow through the AND gate
resistor, through the diode, and through the OR gate resistor.
If we assume that all resistors are of equal value (typically, they are), they
will act as a voltage divider and equally share the +5 volt supply voltage. The
OR gate diode will insert its small loss into the system, and the output voltage
will be about 2.1 to 2.2 volts. If both AND gates have logic 1 inputs, the output
voltage can rise to about 2.8 to 2.9 volts. Clearly, this is in the "forbidden
zone," which is not supposed to be permitted.
If we go one step further and connect the outputs of two or more of these
structures to another AND gate, we will have lost all control over the output
voltage; there will always be a reverse-biased diode somewhere blocking the
input signals and preventing the circuit from operating correctly. This is why
Diode Logic is used only for single gates, and only in specific circumstances.
Resistor-Transistor Logic
Consider the most basic transistor circuit, such as the one shown to the left.
We will only be applying one of two voltages to the input I: 0 volts (logic 0) or
+V volts (logic 1). The exact voltage used as +V depends on the circuit design
parameters; in RTL integrated circuits, the usual voltage is +3.6v. We'll assume
an ordinary NPN transistor here, with a reasonable dc current gain, an emitterbase forward voltage of 0.65 volt, and a collector-emitter saturation voltage no
higher than 0.3 volt. In standard RTL ICs, the base resistor is 470 and the
collector resistor is 640 .
When the input voltage is zero volts (actually, anything under 0.5 volt),
there is no forward bias to the emitter-base junction, and the transistor does not
conduct. Therefore no current flows through the collector resistor, and the
output voltage is +V volts. Hence, a logic 0 input results in a logic 1 output.
When the input voltage is +V volts, the transistor's emitter-base junction
will clearly be forward biased. For those who like the mathematics, we'll
assume a similar output circuit connected to this input. Thus, we'll have a
voltage of 3.6 - 0.65 = 2.95 volts applied across a series combination of a 640
output resistor and a 470 input resistor. This gives us a base current of:
2.95v / 1110 = 0.0026576577 amperes = 2.66 ma.
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RTL is a relatively old technology, and the transistors used in RTL ICs have a dc
forward current gain of around 30. If we assume a current gain of 30, 2.66 ma base
current will support a maximum of 79.8 ma collector current. However, if we drop
all but 0.3 volts across the 640 collector resistor, it will carry 3.3/640 = 5.1 ma.
Therefore this transistor is indeed fully saturated; it is turned on as hard as it can be.
With a logic 1 input, then, this circuit produces a logic 0 output. We have
already seen that a logic 0 input will produce a logic 1 output. Hence, this is a
basic inverter circuit.
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The RTL gate shown above will work, but has a problem due to possible
signal interactions through the multiple input resistors. A better way to
implement the NOR function is shown to the left.
Here, each transistor has only one input resistor, so there is no interaction
between inputs. The NOR function is performed at the common collector
connection of all transistors, which share a single collector load resistor.
This is in fact the pattern for all standard RTL ICs. The very commonlyused µL914 is a dual two-input NOR gate, where each gate is a two-transistor
version of the circuit to the left. It is rated to draw 12 ma of current from the
3.6V power supply when both outputs are at logic 0. This corresponds quite
well with the calculations we have already made.
Standard fan-out for RTL gates is rated at 16. However, the fan-in for a
standard RTL gate input is 3. Thus, a gate can produce 16 units of drive current
from the output, but requires 3 units to drive an input. There are low-power
versions of these gates that increase the values of the base and collector
resistors to 1.5K and 3.6K, respectively. Such gates demand less current, and
typically have a fan-in of 1 and a fan-out of 2 or 3. They also have reduced
frequency response, so they cannot operate as rapidly as the standard gates. To
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As we can see from the above calculations, the amount of current provided
to the base of the transistor is far more than is necessary to drive the transistor
into saturation. Therefore, we have the possibility of using one output to drive
multiple inputs of other gates, and of having gates with multiple input resistors.
Such a circuit is shown to the right.
In this circuit, we have four input resistors. Raising any one input to +3.6
volts will be sufficient to turn the transistor on, and applying additional logic 1
(+3.6 volt) inputs will not really have any appreciable effect on the output
voltage. Remember that the forward bias voltage on the transistor's base will
not exceed 0.65 volt, so the current through a grounded input resistor will not
exceed 0.65v/470 = 1.383 ma. This does provide us with a practical limit on
the number of allowable input resistors to a single transistor, but doesn't cause
any serious problems within that limit.
get greater output drive capabilities, buffers are used. These are typically
inverters which have been designed with a fan-out of 80. They also have a fanin requirement of 6, since they use pairs of input transistors to get increased
drive.
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We can get a NAND function in either of two ways. We can simply invert
the inputs to the NOR/OR gate, thus turning it into an AND/NAND gate, or we
can use the circuit shown to the right.
In this circuit, each transistor has its own separate input resistor, so each is
controlled by a different input signal. However, the only way the output can be
pulled down to logic 0 is if both transistors are turned on by logic 1 inputs. If
either input is a logic 0 that transistor cannot conduct, so there is no current
through either one. The output is then a logic 1. This is the behavior of a
NAND gate. Of course, an inverter can also be included to provide an AND
output at the same time.
The problem with this NAND circuit stems from the fact that transistors are
not ideal devices. Remember that 0.3 volt collector saturation voltage? Ideally
it should be zero. Since it isn't, we need to look at what happens when we
"stack" transistors this way. With two, the combined collector saturation
voltage is 0.6 volt -- only slightly less than the 0.65 volt base voltage that will
turn a transistor on.
If we stack three transistors for a 3-input NAND gate, the combined
collector saturation voltage is 0.9 volt. This is too high; it will promote
conduction in the next transistor no matter what. In addition, the load presented
by the upper transistor to the gate that drives it will be different from the load
presented by the lower transistor. This kind of unevenness can cause some odd
problems to appear, especially as the frequency of operation increases. Because
of these problems, this approach is not used in standard RTL ICs.
Diode-Transistor Logic
As we said in the page on diode logic, the basic problem with DL gates is
that they rapidly deteriorate the logical signal. However, they do work for one
stage at a time, if the signal is re-amplified between gates. Diode-Transistor
Logic (DTL) accomplishes that goal.
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The gate to the right is a DL OR gate followed by an inverter such as the
one we looked at in the page on resistor-transistor logic. The OR function is
still performed by the diodes. However, regardless of the number of logic 1
inputs, there is certain to be a high enough input voltage to drive the transistor
into saturation. Only if all inputs are logic 0 will the transistor be held off.
Thus, this circuit performs a NOR function.
The advantage of this circuit over its RTL equivalent is that the OR logic is
performed by the diodes, not by resistors. Therefore there is no interaction
between different inputs, and any number of diodes may be used. A
disadvantage of this circuit is the input resistor to the transistor. Its presence
tends to slow the circuit down, thus limiting the speed at which the transistor is
able to switch states.
At first glance, the NAND version shown on the left should eliminate this
problem. Any logic 0 inputs will immediately pull the transistor base down and
turn the transistor off, right?
Well, not quite. Remember that 0.65 volt base input voltage for the
transistor? Diodes exhibit a very similar forward voltage when they're
conducting current. Therefore, even with all inputs at ground, the transistor's
base will be at about 0.65 volt, and the transistor can conduct.
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To solve this problem, we can add a diode in series with the transistor's base
lead, as shown to the right. Now the forward voltage needed to turn the
transistor on is 1.3 volts. For even more insurance, we could add a second
series diode and require 1.95 volts to turn the transistor on. That way we can
also be sure that temperature changes won't significantly affect the operation of
the circuit.
Either way, this circuit will work as a NAND gate. In addition, as with the
NOR gate, we can use as many input diodes as we may wish without raising
the voltage threshold. Furthermore, with no series resistor in the input circuit,
there is less of a slowdown effect, so the gate can switch states more rapidly
and handle higher frequencies. The next obvious question is, can we rearrange
things so the NOR gate can avoid that resistor, and therefore switch faster as
well?
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The answer is, Yes, there is. Consider the circuit shown to the left. Here we
use separate transistors connected together. Each has a single input, and
therefore functions as an inverter by itself. However, with the transistor
collectors connected together, a logic 1 applied to either input will force the
output to logic 0. This is the NOR function.
We can use multiple input diodes on either or both transistors, as with the
DTL NAND gate. This would give us an AND-NOR function, and is useful in
some circumstances. Such a construction is also known an an AOI (for ANDOR-INVERT) circuit.