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Floating-Body Memory Serves High-Density Memory Applications
Dr. Pierre C. Fazan, chairman and chief technology officer, Innovative Silicon S.A.
Scaling the conventional 1-transistor/1-capacitor (1T/1C) dynamic-random-access-memory
(DRAM) bit cell below the 40-nm-node dimension represents a serious technical challenge.
Indeed, DRAM-capacitor materials and integration, contacts, and device aspect ratios are all
approaching manufacturing limits. No obvious scaling path exists below 30 nm for the 1T/1C
bit cell. Recently, new memory concepts have been proposed to address these multiple
issues. The capacitor-less DRAM or floating-body (FB) memory cell is one of the leading
contenders to replace DRAM memories for standalone mass-storage applications. This new
technology is simple and uses only conventional materials. It is therefore fully compatible
with CMOS processes. Following the introduction of a technology exploiting a bipolarjunction-transistor (BJT) operation and its recent evolution toward three-dimensional (3D)
devices, low-voltage operation, and bulk silicon implementation, capacitor-less DRAM cells
are now well suited to replace standalone DRAM cells in sub-40-nm memories.
History and Principles of Operation
Capacitor-less DRAM technologies have significantly evolved over the years. The first
attempt at exploiting a single MOS transistor to store information was made by Sasaki et al.
of Fujitsu in 1978. They integrated a p-channel-metal-oxide-semiconductor (PMOS) transistor
with silicon-on-sapphire (SOS). By exploiting the FB effect of a single n-channel MOS
(NMOS) silicon-on-insulator (SOI) transistor, a simpler and denser structure was proposed
by Tack et al. of IMEC in 1990. The device operations described by these researchers were,
however, incompatible with selective read/write operations and memory-array integration.
That explains why the technical developments in this area stopped after these two first
attempts.
In 2001, Okhonin et al. of Innovative Silicon demonstrated that by properly pulsing
the device gate and drain, a selective write/read operation was possible. This opened the
door to memory-array implementation. This successful array-compatible operation was also
mentioned in 2002 by Ohsawa et al. of Toshiba. These first attempts at building memory
arrays used the MOS transistor to pass current and create a charge in the floating body
using impact ionization. Although memory functionality can be demonstrated, the amount of
charge created is insufficient to yield a robust and manufacturable memory device.
By exploiting the bipolar transistor intrinsic to the SOI MOS structure (BJT operation
as illustrated in Figure 1), Okhonin et al. developed a technology exhibiting a higher signalto-noise ratio, longer retention time, better scaling ability, and full compatibility with future
fully depleted (FD) 3D devices. More recently, Innovative Silicon unveiled a low-voltage
operating mode and the integration of 3D memory structures on bulk silicon wafers. By
using vertical device junction isolation, a floating-body structure can be realized on bulk
silicon without the need for SOI wafers. By optimizing the writing and reading operations,
bit-cell operation with Vdd values lower than 1 V is demonstrated. This ultra-dense and
ultra-low-cost memory—combined with low-voltage operation—is expected to replace
standalone DRAMs for high-density applications that meet DDR specifications. In addition,
the floating-body memory performance allows capacitor-less DRAM cells to replace
embedded DRAMs or embedded SRAMs built with logic processes. This drastically increases
the market opportunities for such a technology.
Figure 1: BJT floating-body memory exploits a BJT operation.
MOS transistor
Floating body
Standalone DRAM Replacement
The FB memory/capacitor-less DRAM bit cell and operating principles can be used as
a standalone DRAM replacement. Cell sizes of 4F2 to 8F2 (F being the minimum feature size
of the technology) are possible for planar transistors (see Figure 2). The cell area depends
on the layout details. The cell becomes smaller when adjacent cells share source and drain
terminals. It becomes larger when one or two of the source and drain terminals of adjacent
cells are separated.
Figure 3 shows scanning-electron-microscopy (SEM) images of 6F2 capacitor-less
DRAM bit cells implemented in a 50-nm, low-leakage memory-type technology for a
planar/SOI and 3D/bulk-silicon implementation. As can be seen in the pictures, two adjacent
cells share a common bit line or drain contact and have separated source nodes. Word and
source lines run parallel to each other while bit lines are orthogonal. Such memory cells
integrated with a low-leakage, memory-type process exhibit a typical retention time of a few
seconds (see Figure 4).
Figure 2: Here, floating-body memory is shown in various bit-cell layouts.
Figure 3: These images show 6F2 standalone, floating-body-memory, bit-cell cross
sections.
Figure 4: Shown is typical standalone, floating-body-memory device retention
time.
Scaling, Roadmap, and Challenges
At 40 nm and below, excessive device leakage resulting from aggressive device
scaling severely affects both standby power and retention for DRAM technologies. This has
prompted 3D device structures to enter the various standalone memory-technology
roadmaps. These 3D structures also provide a benefit to FB memory cells. They allow FB
memories to be built on bulk silicon wafers and therefore drastically reduce chip cost. In
addition, they enable source and drain doping profile engineering to control and improve cell
electrical performance. Due to its unique compatibility with fully depleted devices, FB
memory technology is fully portable to all forms of 3D device architectures, such as the
following: fin-shaped field-effect transistors (FinFETs); multiple-gate FETs (MuGFETs); surrounding
gate transistors (SGTs); and tri-gate, vertical double-gate, and gate-all-around structures.
For example, Figure 5 shows the programming window and retention time of an
experimental 11-nm FinFET device. The device SEM cross section is shown in Figure 6. In a
FinFET- or Tri-Gate-based structure, the charge accumulates under the transistor gate and
the current flows in the middle of the fin structure. The charge is stored throughout the fin,
permitting excellent control of the current.
Figure 5: Here are the programming window (left) and retention time
(right) for an 11-nm FinFET FB memory.
Figure 6: This is the cross section for a FinFET SEM.
The main challenges with FB-memory technologies are achieving the targeted
retention times required by the application, integrating with a low-cost process for 3D
implementations, and operating at low voltages to satisfy all reliability requirements. The
retention times demonstrated in Figure 4 satisfy the requirements for a typical bit cell.
For technology nodes below 40 nm, standard 1T/1C DRAM bit cells present huge
scaling and manufacturing challenges. Due to the simplicity and performance of FB memory
with future 3D structures, it appears to be the ideal candidate to replace standard DRAM bit
cells for future high-density embedded-memory applications.
About the Author
In 2002, Dr. Pierre C. Fazan co-founded Innovative Silicon, developing a new SOI singletransistor memory technology. He acted first as the company’s chief executive officer and is
now chairman and chief technology officer. He has authored or co-authored more than 100
papers and has invented or co-invented more than 190 U.S. patents. He obtained his
physics diploma and PhD degrees at the Swiss Federal Institute of Technology (EPFL) in
1984 and 1988, respectively. Fazan can be reached at [email protected].