Download Requirements for the Data Acquisition and Control

Cryogenic Underground Observatory for Rare Events
Data Acquisition and Control System Requirements
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30/04/2017
Requirements for the Data
Acquisition and Control System
Authors: E. Guardincerri, M. Pallavicini [INFN Genova]
Document Version: 1.0
Date: 28 June 2004
Cryogenic Underground Observatory for Rare Events
Data Acquisition and Control System Requirements
Version: 1.0
30/04/2017
Table of Contents
SECTION A: DOCUMENT CONTENT.............................................................................................. 3
SECTION B: GENERAL DESCRIPTION OF THE SYSTEM AND SUB-SYSTEMS
DEFINITIONS........................................................................................................................................ 4
B.1 INTRODUCTION .............................................................................................................................. 4
B.2 THE CUORE DIGITIZER BOARD ...................................................................................................... 4
B.3 THE DATA ACQUISITION HARDWARE ............................................................................................ 7
B.4 THE TRIGGERING PHILOSOPHY ....................................................................................................... 7
B.5 THE SLOW CONTROL SYSTEM ........................................................................................................ 8
B.6 THE DATA ACQUISITION SOFTWARE.............................................................................................. 8
SECTION C: SYSTEM REQUIREMENTS ........................................................................................ 9
C.1 REQUIREMENTS FOR THE INPUT SIGNAL ......................................................................................... 9
C.2 REQUIREMENTS FOR THE AUXILIARY INPUT SIGNAL ....................................................................... 9
C.3 REQUIREMENTS FOR THE VME DIGITIZER.................................................................................... 10
C.4 CONNECTORS ............................................................................................................................... 10
C.5 ELECTRICAL PROTECTIONS .......................................................................................................... 10
C.6 POWER SUPPLIES .......................................................................................................................... 10
C.7 REQUIREMENTS FOR SLOW CONTROL SYSTEM ............................................................................ 11
C.8 REQUIREMENTS FOR ONLINE COMPUTING AND NETWORK ............................................................ 12
Cryogenic Underground Observatory for Rare Events
Data Acquisition and Control System Requirements
Version: 1.0
30/04/2017
SECTION A: DOCUMENT CONTENT
This document describes the scientific and experimental requirements of the Cuore
Data Acquisition and Control System.
Here and throughout the document we define as Data Acquisition and Control System
(DACS) all the hardware equipement and software programs that are needed to:
a) digitize the analogue pulses provided by the front end cards
b) control the data taking operations
c) monitor the operations online.
The document is structured as follows: sections B.1 - B.6 give a very brief
description of the system1 and define a set of sub-systems.
Sections C.3 - C.8 describe the specific requirements for all subsystems.
This is a live document. The technical specification and the requirements of the
system will be continuously included in the latest version of the document. It may
also be found at http://www.ge.infn.it/~pallas/Cuore/Requirements1_0.pdf
1
We stress the fact that this is neither a technical document nor a detailed description of the system. In
fact, the general description section is given only to clarify the requirements and allow the reader to
understand their meaning and their impact on Cuore science.
Cryogenic Underground Observatory for Rare Events
Data Acquisition and Control System Requirements
Version: 1.0
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SECTION B: GENERAL DESCRIPTION OF THE SYSTEM
AND SUB-SYSTEMS DEFINITIONS
B.1 Introduction
In this section we briefly describe the Cuore DACS.
Being the DACS project at an early stage of development, we do not give here any
technical detail; in fact, we focus on the system elements that we think the reader
should know to be able to understand the requirements reported in section C and,
most important, to understand whether these requirements are appropriate for Cuore
science.
As stated in the previous section, in this document we call “Data Acquisition and
Control System”, all electronics, computers and software that are used to convert the
analogue output of the warm front end boards into digital data on computer disk; we
also include in the system what is usually called the “slow control system”, i.e. the
hardware and software needed to control detector bias, set thresholds or parameters
into the electronics system, and, possibly, part of the cryogenics control system.
The system is basically composed of:
a) A set of digital readout boards (CDBs, Cuore Digitizer Boards). These boards
are VME standard and they perform continuous sampling of analogue signals
coming from the warm front end cards. The CDBs are described in section B.2
In the current baseline we need about 85 boards to read the foreseen 1000
crystals.
b) A set of VME crates (about 9 in the current baseline) connected via optical
link with a set of DAQ computers. This sub-system is described in section B.3
c) The triggering system, described in section B.4
d) The slow control system that takes care of detector monitor and control (see
section B.5 )
e) The data acquisition software
B.2 The Cuore Digitizer Board
The Cuore Digitizer Board (CDB) performs continuous ADC conversion of the
analogue signal coming from the front end cards.
Each CDB has a standard 6U VME format, 12 independent inputs and is fully
programmable via VME interface.
Each channel is equipped with an 18 bit ADC that accepts a dynamic range from -10
V up to 10 V. The sampling speed is programmable up to a maximum of 10 KHz.
Each channel is completely independent and the sampling circuit has zero dead time.
In order to reduce the cross talk noise generated by digital signals in the VME board
and backplane the analogue section of the board are built as independent piggy-back
boards (PB).
A block diagram of a piggy back board is provided in Figure 2.
Each channel is equipped with 2 input connectors: the real analogue input that brings
the signal to the sampling ADC and an auxiliary input that can be used for triggering
purposes. This auxiliary input is connected to a discriminator with a VME
programmable threshold. The CDB has auto-triggering capability through the
Cryogenic Underground Observatory for Rare Events
Data Acquisition and Control System Requirements
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auxiliary input, but it can be used also as a continuous digitizer without any trigger.
See section B.4 for details on trigger.
The analogue input is differential. We are planning to use double Lemo connector (2
signal wires with ground shielding) but the final decision on connector will be taken
in the future.
The boards support A16/A32/D32 data transfer and allow block transfer at standard
VME speed.
The CDB block diagram is depicted in Figure 1.
F
R
O
N
T
P
A
N
E
L
FPGA
ADCs
FPGA
V
M
E
FPGA
ADCs
FPGA
ADCs
Figure 1 – Block diagram of the CDB
RAM
B
U
S
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Data Acquisition and Control System Requirements
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PIGGY BACK
ANALOGUE
INPUT
G=1
ADC
G=1
ADC
DATA + FLAGS
G=1
ADC
G=1
ADC
trigger flag
input buffers
Main
Board
THRESHOLDS +
SAMPLING RATES
(programmable)
thresholds
Front end boards
FPGA
AUXILIARY INPUT
threshold discriminators
Figure 2 – Block diagram of the PB
Input connectors
ADCs
FPGA
Figure 3 - The piggy-back layout. Each piggy back handles 4 channels with both the analogue
input and auxiliary input (see text). A single FPGA controls the sampling sequence and
communication with the main board.
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Data Acquisition and Control System Requirements
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B.3 The Data Acquisition Hardware
The data acquisition hardware is composed of:
a) several VME crates (9 in case we have to read 1000 channels, twice as much
with 2000 channels).
b) a set of computers that communicate with the VME crates via optical link
c) a network infrastructure that allow communication among computers
The conceptual structure of the system is depicted in
Figure 4.
Figure 4 - Conceptual block diagram of the DACS hardware.
Each VME crate is controlled and read by a dedicated PC connected with a PCI-VME
interface. The connection is optical and guarantees electrical decoupling. The
software running on each PC collects the data, performs the first level trigger (if this
is required) and transfers the data to the system consoles, where event building and
data storage occur. The system consoles (whose number is not critical and will be
defined in the future) will also provide the user interface. One of the computers will
also control the I2C or serial bus that will allow communication with the power
supplies and with the front end cards. The details of the protocol with the front end
electronics and with the power supplies will be defined in the future.
All computers are connected each other via a standard network switch. Although a
simple 100 Mbit would be adequate for Cuore needs, we will probably use Gbit
optical links.
B.4 The triggering philosophy
The goal of the triggering system is to identify the useful pulses in the random
background.
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The system is designed to perform this operation in three possible ways that we call
here “modes”: hardware trigger mode (HTM), hardware flag mode (HFM) and the
software trigger mode (STM).
We describe here briefly these three modes:
HTM: In this mode the trigger is done with an hardware analogue circuit built in the
front end cards. When a trigger occurs, a large (>100 mV) pulse is generated and
delivered to the CDB. The CDB channel is equipped via an additional input for this
signal and a programmable discriminator (there are therefore two connectors for each
channel: one for the real signal and one for this triggering signal).
The digitized data is then transferred to the DAQ computers in a user programmable
window around the trigger (typical window time width will be several seconds,
starting well before the trigger signal). No other data are acquired in this mode.
HFM: In this mode the data around an HT is only flagged by the CDB but it is
transferred to the DAQ computers anyway. Only a software algorithm, possibly but
not necessarily using the HF, will take the final decision to store the data or not.
STM: In this case all data is read continuously and the triggering algorithms is done
only with software.
The system will support all these 3 modes. HFM and STM can be run at the same
time to allow cross check. It will also be possible to have HTM with very low
threshold refined by the STM.
B.5 The Slow Control System
Several devices must be controlled and monitor during data taking:
a) Front end cards
b) Filter cards
c) Heater pulser
d) Power supplies
e) Cryogenic system
f) Environment sensors
Each of these devices will be periodically monitor during data taking and their status
can be correlated with data through the system data base.
The user interface will allow the user to control the whole system.
B.6 The Data Acquisition Software
The data acquisition software will be completely custom made, written in C++ and
based on the root package (http://root.cern.ch).
The structure of the software will be described in a future version of the document.
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Data Acquisition and Control System Requirements
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SECTION C: SYSTEM REQUIREMENTS
C.1 Requirements for the input signal
In this section we refer to the properties of the signal as it comes out from the warm
front end boards: we neglect the previous stages of the acquisition chain in which the
signal is generated, amplified and shaped.
The typical shape of the signal due to an event is shown in Figure 5.
Figure 5 – Typical shape of a signal due to an event.
The main features of the signal are summarized in the following list of parameters:

Amplitude of the signal from the front-end: max 10 V

Rise time: 30 ms

Fall time: variable, from 30 ms to several hundreds of ms
C.2 Requirements for the auxiliary input signal
To be done
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C.3 Requirements for the VME digitizer
The following table summarize the digitizer boards requirements.
Parameter
Channels
ADC bits
Sampling speed
ADC conv. time
Baseline value
Noise
Input range
Trigger thresh.
Trigger DAC bits
Min
6
16
0.001
10
0.
?
0.
?
-
Max
12
18
10
10.
150
+10.
?
-
Baseline
12
18
1
0.4
150
?
8
Units
KHz
s
V
V (2)
V
mV
-
Notes
-
Table 1: List of digitizer board parameters.
The board must also provide the following features:

Independent sampling of each cannel without dead time.

All the channels must be auto triggering, with programmable threshold
on the incoming signal. A double threshold might be desirable (to be
defined…)

Continuous sampling within the allowed sampling rate range
C.4 Connectors
To be done.
C.5 Electrical protections
To be done.
C.6 Power supplies
Most likely the digitizer board will not be powered by standard switching VME
power supplies, but a custom made low noise power supply system will be needed.
According to a preliminary and rough esteem, the power required to operate each
CDB is about 8 W.
The power will be distributed by a DC remote power supply system that is described
elsewhere.
The DAQ VME crates will receive power from DC ±24 (or possibly ±15) V lines.
The standard VME values ±12 V and +5V will be done locally.
It would be nice to use the same power supply system for front end cards, filter cards
and CDBs.
2
The quoted number is just a reference r.m.s. voltage noise value integrated over the signal bandwidth.
This value corresponds to the 10 V input range of ADC divided by 2 16.
Cryogenic Underground Observatory for Rare Events
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At present two options for distributing the power supply to the boards are under
analysis:
 The external ±24 (±15) V line could feed a dedicated board whose working
principle is sketched in Figure 6. Hence the power supply could be distributed
to the CDBs through some auxiliary lines located on the backplane of the
VME crate. The voltage supply levels needed by the CDBs could be generated
locally by linear regulators placed on the boards themselves. This solution
requires to use non standard VME crates endowed with additional connectors
and power distribution lines on the backplane
± 24 V
DC/DC
DC/DC
+5V
± 12 V
to the
optical
interface
board
± 15 V
+6V
to the
aux
connector
Figure 6- Conceptual sketch of the power supply distribution board

The external ±24 (±15) V line could feed directly each CDB through a
standard connector on the backplane: each board would then generate the
voltage supplies needed by linear regulators. A dedicated board will be
anyway necessary to provide the power supply for the optical interface board.
The choice to employ linear regulators is dictated by the severe constraints the
acquisition system must satisfy in terms of noise. Its drawback is the large waste
of power due to the intrinsically low efficiency of linear regulators’ operation
mode: the power actually dissipated by the system could be even thrice the
amount needed for its operation.
As a consequence, the cooling system for the VME crates must be dimensioned in
order to provide a cooling power of at least 20 W/CDB.
A design of the power distribution setup will be made after some tests aiming to
esteem the contribution of different voltage regulators to noise.
C.7 Requirements for Slow Control System
As described in section B.5 the Slow Control System is devoted to the control and/or
monitor of the following sub-systems:
Cryogenic Underground Observatory for Rare Events
Data Acquisition and Control System Requirements
a)
b)
c)
d)
e)
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Front end cards
Filter cards
Heater pulser
Power supplies
Cryogenic system
a. Estimated number of monitor parameters:
i. 5 flow meters
ii. 20 warm termometers
iii. 60 special channels (NTD used as termometers for detector)
iv. 25 pressure gauges
v. 5 level meters
b. Actuators
i. 4 compressors
ii. Chiller
iii. 8 pumps
c. Valves
i. 40 valves (most of them ON/OFF)
f) Environment sensors
a. 20 parameters
b. Monitor of Cuore chiller (10 parameters)
All sub-systems, except maybe the cryostat (TBD), are controlled via I2C with optical
link or via another optically decoupled serial protocol. The protocols are always
master-slave, with the Slow Control PCs being always the transaction master. No
asynchronous signal can therefore be issued by the slaves and alarms can be identified
only through polling. In case a limited number of asynchronous alarms had to be
handled, this should not be done via I2C link, but should be done via digital TTL or
NIM signals that will be interfaced to a dedicated sub-system.
The approximate number of parameters, the number of I2C addresses and the
approximate maximum polling frequency that must be handled by the system is
described in
Table 2.
Sub-System
Front End
Filters
Heater Pulser
Power supply
Cryostat
Number of
devices
1000
334
100
48+8=56
N° of I2C
addresses
1000
1000
100
56
N° of
parameters
6000
1000
1600
undefined
Monitor
frequency
< 0.02 Hz
< 0.02 Hz
< 0.02 Hz
< 0.02 Hz
Table 2: List of I2C devices that the slow control system must control and monitor. The Table
reports the number of I2C devices and the maximum frequency at which these devices must be
monitored by the system.
C.8 Requirements for online computing and network
The current computer technology is adequate for CUORE needs. The system will be
designed to allow full acquisition without any data filtering assuming the figures
Cryogenic Underground Observatory for Rare Events
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shown in Table 3. Remote system control is foreseen. The system will be also
dimensioned to allow online event analysis.
Parameter
Channels
Event Rate per Channel
Sampling Rate per Channel
Samples per Pulse
Bytes per Pulse
Data throughput with STM
Table 3: Data throughput parameters.
Min
1000
0.001
1000
4000
-
Max
2000
1
5
10000
40000
3.2
Baseline
1000
0.01
1
5000
20000
0.2
Units
Hz
KHz
Long Words
Bytes
Mb/s