NLAS52231 Ultra-Low 0.4 W Dual SPDT Analog Switch with
... without incurring significant leakage. This feature provides added protection against undesirable leakage or damage to the device in the event that an incoming audio signal spikes above its nominal level. The NLAS52231 features a wide V CC operating range, 1.65 V−4.5 V. It is capable of interfacing ...
... without incurring significant leakage. This feature provides added protection against undesirable leakage or damage to the device in the event that an incoming audio signal spikes above its nominal level. The NLAS52231 features a wide V CC operating range, 1.65 V−4.5 V. It is capable of interfacing ...
SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs ADAU1401A
... The ADAU1401A is a complete, single-chip audio system with 28-/56-bit audio DSP, ADCs, DACs, and microcontroller-like control interfaces. Signal processing includes equalization, crossover, bass enhancement, multiband dynamics processing, delay compensation, speaker compensation, and stereo image wi ...
... The ADAU1401A is a complete, single-chip audio system with 28-/56-bit audio DSP, ADCs, DACs, and microcontroller-like control interfaces. Signal processing includes equalization, crossover, bass enhancement, multiband dynamics processing, delay compensation, speaker compensation, and stereo image wi ...
OPA2684 Low-Power, Dual Current-Feedback OPERATIONAL AMPLIFIER FEATURES
... freedom from amplifier bandwidth interaction. This allows frequency response peaking elements to be added, multiple input inverting summing circuits to have greater bandwidth, and low-power line drivers to meet the demanding requirements of studio cameras and broadcast video. The output capability o ...
... freedom from amplifier bandwidth interaction. This allows frequency response peaking elements to be added, multiple input inverting summing circuits to have greater bandwidth, and low-power line drivers to meet the demanding requirements of studio cameras and broadcast video. The output capability o ...
H7GP/H7HP Total Counter/Time Counter
... 2. Only a non-voltage input (NPN transistor) is possible for the key protection input. The key protection input will be a non-voltage input even if the NPN/PNP input mode is set to PNP. Key protection is used to prohibit operating the Reset Key. The reset input terminals will still be functional. ...
... 2. Only a non-voltage input (NPN transistor) is possible for the key protection input. The key protection input will be a non-voltage input even if the NPN/PNP input mode is set to PNP. Key protection is used to prohibit operating the Reset Key. The reset input terminals will still be functional. ...
AD5379 英文产品数据手册下载
... REG0, REG1, address to WR rising edge setup time. REG0, REG1, address to WR rising edge hold time. CS pulse width low. WR pulse width low. CS to WR falling edge setup time. WR to CS rising edge hold time. Data to WR rising edge setup time. Data to WR rising edge hold time. WR pulse width high. Minim ...
... REG0, REG1, address to WR rising edge setup time. REG0, REG1, address to WR rising edge hold time. CS pulse width low. WR pulse width low. CS to WR falling edge setup time. WR to CS rising edge hold time. Data to WR rising edge setup time. Data to WR rising edge hold time. WR pulse width high. Minim ...
Low Distortion Differential ADC Driver AD8138
... performance ADCs, preserving the low frequency and dc information. The common-mode level of the differential output is adjustable by a voltage on the VOCM pin, easily level-shifting the input signals for driving single-supply ADCs. Fast overload recovery preserves sampling accuracy. The AD8138 disto ...
... performance ADCs, preserving the low frequency and dc information. The common-mode level of the differential output is adjustable by a voltage on the VOCM pin, easily level-shifting the input signals for driving single-supply ADCs. Fast overload recovery preserves sampling accuracy. The AD8138 disto ...
AD1955 数据手册DataSheet下载
... can be used with any word length up to 24 bits. In this mode, it is the responsibility of the DSP to ensure that the left data is transmitted with the first LRCLK pulse after RESET, and that synchronism is maintained from that point forward. In Right-Justified Mode (16 bits shown), LRCLK is high for ...
... can be used with any word length up to 24 bits. In this mode, it is the responsibility of the DSP to ensure that the left data is transmitted with the first LRCLK pulse after RESET, and that synchronism is maintained from that point forward. In Right-Justified Mode (16 bits shown), LRCLK is high for ...
FEATURES DESCRIPTION D
... (Machine Model) . . . . . . . . . . . . . . . . . . . . . . . . . . 200V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at ...
... (Machine Model) . . . . . . . . . . . . . . . . . . . . . . . . . . 200V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at ...
LTC699 - Microprocessor Supervisory Circuit
... as RESET is inactive. When either a high-to-low or low-tohigh transition occurs at the WDI pin prior to time-out, the watchdog time is reset and begins to time out again. To ensure the watchdog time does not time out, either a highto-low or low-to-high transition on the WDI pin must occur at or less ...
... as RESET is inactive. When either a high-to-low or low-tohigh transition occurs at the WDI pin prior to time-out, the watchdog time is reset and begins to time out again. To ensure the watchdog time does not time out, either a highto-low or low-to-high transition on the WDI pin must occur at or less ...
API9221EV1 User Guide Issue 3
... CAUTION: Do not connect a Lithium Ion cell before first removing the link CAP SW, or setting it to the “0F” position. (A cell is not required for the tests described here.) Suitable test equipment is given in the table below. The oscilloscope is optional, but gives a display of the output voltage ag ...
... CAUTION: Do not connect a Lithium Ion cell before first removing the link CAP SW, or setting it to the “0F” position. (A cell is not required for the tests described here.) Suitable test equipment is given in the table below. The oscilloscope is optional, but gives a display of the output voltage ag ...
MAX1840/MAX1841 Low-Voltage SIM/Smart Card Level Translators in µMAX General Description
... multivoltage systems. These devices operate with logic supply voltages between +1.4V and +5.5V on the controller side (DVCC) and between +1.7V and +5.5V on the card side (VCC). The total supply current (IDVCC + IVCC) is 1µA while operating in an idle state (see Electrical Characteristics). Figure 1 ...
... multivoltage systems. These devices operate with logic supply voltages between +1.4V and +5.5V on the controller side (DVCC) and between +1.7V and +5.5V on the card side (VCC). The total supply current (IDVCC + IVCC) is 1µA while operating in an idle state (see Electrical Characteristics). Figure 1 ...
MAX13442E/MAX13443E/MAX13444E ±15kV ESD-Protected, ±80V Fault-Protected, Fail-Safe RS-485/J1708 Transceivers General Description
... The MAX13442E/MAX13444E are fault-protected RS-485 and J1708 transceivers that feature ±80V protection from signal faults on communication bus lines. The MAX13442E/MAX13444E feature a reduced slew-rate driver that minimizes EMI and reflections, allowing error-free transmission up to 250kbps. The MAX ...
... The MAX13442E/MAX13444E are fault-protected RS-485 and J1708 transceivers that feature ±80V protection from signal faults on communication bus lines. The MAX13442E/MAX13444E feature a reduced slew-rate driver that minimizes EMI and reflections, allowing error-free transmission up to 250kbps. The MAX ...
WT 1600 Total Solution Numerical, Waveform, and Trend Displays
... rpms (requires the optional motor evaluation function) • Measurement of rapidly fluctuating secondary voltage and lamp current when a light is turned on ...
... rpms (requires the optional motor evaluation function) • Measurement of rapidly fluctuating secondary voltage and lamp current when a light is turned on ...
Interfacing to MM74HC High-Speed CMOS Logic Interfacing to
... systems may be necessary. If these systems operate within the metal-gate CMOS supply range, interfacing MM74HC to them is similar to interfacing to CD4000 operating at a higher supply. In rugged industrial environments, care may be required to ensure that large transients do not harm the CMOS logic. ...
... systems may be necessary. If these systems operate within the metal-gate CMOS supply range, interfacing MM74HC to them is similar to interfacing to CD4000 operating at a higher supply. In rugged industrial environments, care may be required to ensure that large transients do not harm the CMOS logic. ...
AD5313 数据手册DataSheet 下载
... Reference Input Pin for DAC B. It may be configured as a buffered or an unbuffered input, depending on the state of the BUF B pin. It has an input range from 0 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. Reference Input Pin for DAC A. It may be configured as a buffered or an un ...
... Reference Input Pin for DAC B. It may be configured as a buffered or an unbuffered input, depending on the state of the BUF B pin. It has an input range from 0 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. Reference Input Pin for DAC A. It may be configured as a buffered or an un ...
9.2 Schmitt Trigger
... Schmitt is hampered by its narrow supply range, 阻抗 limited interface capability, low input impedance and unbalanced output characteristics. The Schmitt trigger could be built from discrete devices to satisfy a particular parameter, but this is a careful and sometimes time-consuming design. ...
... Schmitt is hampered by its narrow supply range, 阻抗 limited interface capability, low input impedance and unbalanced output characteristics. The Schmitt trigger could be built from discrete devices to satisfy a particular parameter, but this is a careful and sometimes time-consuming design. ...
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... The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level 1 type) and IEEE Std 1284-II (level ...
... The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level 1 type) and IEEE Std 1284-II (level ...
DS1374 I C, 32-Bit Binary Counter Watchdog RTC with
... ICCA—SCL clocking at max frequency = 400kHz. Specified with I2C bus inactive. Measured with a 32.768kHz crystal attached to the X1 and X2 pins. WDSTR = 1. BBSQW = 1 is required for operation when VCC is below the power-fail trip point (or absent). CB—total capacitance of one bus line in pF. After th ...
... ICCA—SCL clocking at max frequency = 400kHz. Specified with I2C bus inactive. Measured with a 32.768kHz crystal attached to the X1 and X2 pins. WDSTR = 1. BBSQW = 1 is required for operation when VCC is below the power-fail trip point (or absent). CB—total capacitance of one bus line in pF. After th ...
Flip-flop (electronics)
In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.Flip-flops and latches are used as data storage elements. A flip-flop stores a single bit (binary digit) of data; one of its two states represents a ""one"" and the other represents a ""zero"". Such data storage can be used for storage of state, and such a circuit is described as sequential logic. When used in a finite-state machine, the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal.Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered). Although the term flip-flop has historically referred generically to both simple and clocked circuits, in modern usage it is common to reserve the term flip-flop exclusively for discussing clocked circuits; the simple ones are commonly called latches.Using this terminology, a latch is level-sensitive, whereas a flip-flop is edge-sensitive. That is, when a latch is enabled it becomes transparent, while a flip flop's output only changes on a single type (positive going or negative going) of clock edge.