• Study Resource
  • Explore Categories
    • Arts & Humanities
    • Business
    • Engineering & Technology
    • Foreign Language
    • History
    • Math
    • Science
    • Social Science

    Top subcategories

    • Advanced Math
    • Algebra
    • Basic Math
    • Calculus
    • Geometry
    • Linear Algebra
    • Pre-Algebra
    • Pre-Calculus
    • Statistics And Probability
    • Trigonometry
    • other →

    Top subcategories

    • Astronomy
    • Astrophysics
    • Biology
    • Chemistry
    • Earth Science
    • Environmental Science
    • Health Science
    • Physics
    • other →

    Top subcategories

    • Anthropology
    • Law
    • Political Science
    • Psychology
    • Sociology
    • other →

    Top subcategories

    • Accounting
    • Economics
    • Finance
    • Management
    • other →

    Top subcategories

    • Aerospace Engineering
    • Bioengineering
    • Chemical Engineering
    • Civil Engineering
    • Computer Science
    • Electrical Engineering
    • Industrial Engineering
    • Mechanical Engineering
    • Web Design
    • other →

    Top subcategories

    • Architecture
    • Communications
    • English
    • Gender Studies
    • Music
    • Performing Arts
    • Philosophy
    • Religious Studies
    • Writing
    • other →

    Top subcategories

    • Ancient History
    • European History
    • US History
    • World History
    • other →

    Top subcategories

    • Croatian
    • Czech
    • Finnish
    • Greek
    • Hindi
    • Japanese
    • Korean
    • Persian
    • Swedish
    • Turkish
    • other →
 
Profile Documents Logout
Upload
Document
Document

CircuitI_exp061411496081
CircuitI_exp061411496081

POWER NOTES
POWER NOTES

74LS125 Quad 3
74LS125 Quad 3

... General Description This device contains four independent gates each of which performs a non-inverting buffer function. The outputs have the 3-STATE feature. When enabled, the outputs exhibit the low impedance characteristics of a standard LS output with additional drive capability to permit the dri ...
Lecture 1
Lecture 1

... used to control the action of a circuit; for instance, a typical flip-flop grabs and remembers its input every time the controlling clock rises from logic 0 to logic 1. The square wave is available at the CLK pin. The frequency of the square wave is controlled with two settings. There are four femal ...
SoC_Embedded Processor2
SoC_Embedded Processor2

... – Apply parallelism and/or pipelining to maintain throughput – Useful if enough parallelism exists but latency and area overhead increases ...
ALS-102 Core Logic Board Nuclear Automation Background
ALS-102 Core Logic Board Nuclear Automation Background

... The ALS-102 is designed for autonomous operation, allowing the system level design to maintain the overall integrity of the application whether a fault occurs within the individual board or at the system level. A failure in one of the input, output or communication channels does not impact the other ...
viju
viju

... device are available up to 600V but with limited current. Can be paralleled quite easily for higher current capability.  Internal (dynamic) resistance between drain and source during on state, RDS(ON), , limits the power handling capability of MOSFET. High losses especially for high voltage device ...
TLS810XXX TLS805XXX Product Brief
TLS810XXX TLS805XXX Product Brief

... DSO-8 EP packages. The TLS805 is a 50 mA linear voltage regulator available in TSON-10 and DSO-8 packages. The wide input voltage range and the ultra-low quiescent current make it perfectly suitable for supply systems connected permanently to the battery. The family offers various options of feature ...
High-Speed Data Communication LA302Z – 10 GHz Differential
High-Speed Data Communication LA302Z – 10 GHz Differential

Frequency and Voltage Scaling Design
Frequency and Voltage Scaling Design

... On read timing, we simply rely on the system to return read data before the CPU clock that occurs just before the rising edge of HCLK. Advantages: using edge-triggered registers, standard implementation work effectively to assure correct timing, makes automated design-for-test straightforward. Disad ...
ECE124 Digital Circuits and Systems Page 1
ECE124 Digital Circuits and Systems Page 1

TAN-008
TAN-008

... an effective -3dB bandpass frequency range of 960 Hz to 2850 Hz, (see Figure 8). While an LM-324 was utilized as the gain element, it should be noted that almost any amplifier with a reasonably large gain (e.g. >10,000), relatively high input impedance and a moderately high bandwidth (e.g. >100,000 ...
Test Procedure for the LV56801PGEVB Evaluation Board  SANYO Semiconductors
Test Procedure for the LV56801PGEVB Evaluation Board SANYO Semiconductors

White Paper on Secure Integrated Circuits and Systems Project
White Paper on Secure Integrated Circuits and Systems Project

Worksheets
Worksheets

hmrp - Mirus International
hmrp - Mirus International

Power Injector DUO User Guide
Power Injector DUO User Guide

LED770x LED drivers New monolithic step-up family driving LEDs
LED770x LED drivers New monolithic step-up family driving LEDs

... reference voltage, and adapt the boost output voltage to reduce power losses across the current generators. The boost-converter switching frequency is fixed at 630 kHz. This is a good compromise in terms of efficiency and size and cost of the power elements and of the overall application, but it can ...
Nyquist–Shannon sampling theorem
Nyquist–Shannon sampling theorem

... the time-domain, in which inputs and outputs are functions of time, to the frequency-domain, where the same inputs and outputs are functions of complex angular frequency, in radians per unit time. Given a simple mathematical or functional description of an input or output to a system, the Laplace tr ...
REC15_AL / REC25_AL
REC15_AL / REC25_AL

... Off-line system designed with Network editor allowing users to make the electrical scheme of a network. Network elements such as lines, sources, reclosers, transformers, fuses, loads etc. with their parameters can be mapped in the scheme. Once the network data have been entered it is possible to find ...
Reactive & Voltage Maintenance - Joint Proposal
Reactive & Voltage Maintenance - Joint Proposal

... • Bus voltage maintenance is the objective and the performance criteria in proposal aligns incentives with that, • Per interval payment based on fixed base case value sets an annual cap of potential payments, • Method is not complex with a minimum of variables for ISO to manage/collect from telemetr ...
IOSR Journal of Electronics and Communication Engineering (IOSR-JECE)
IOSR Journal of Electronics and Communication Engineering (IOSR-JECE)

... arbitrary images (as in a general-purpose computer display) or fixed images with low information content, which can be displayed or hidden, such as preset words, digits, and 7-segment displays as in a digital clock. They use the same basic technology, except that arbitrary images are made up of a la ...
Document
Document

g/plain
g/plain

... Register  File  tradeoffs   +  Very  fast  (a  few  gate  delays  for  both  read  and  write)   +  Adding  extra  ports  is  straighporward   –    Doesn’t  scale   ...
< 1 ... 1060 1061 1062 1063 1064 1065 1066 1067 1068 ... 1306 >

Immunity-aware programming

When writing firmware for an embedded system, immunity-aware programming refers to programming techniques which improve the tolerance of transient errors in the program counter or other modules of a program that would otherwise lead to failure. Transient errors are typically caused by single event upsets, insufficient power, or by strong electromagnetic signals transmitted by some other ""source"" device.Immunity-aware programming is an example of defensive programming and EMC-aware programming. Although most of these techniques apply to the software in the ""victim"" device to make it more reliable, a few of these techniques apply to software in the ""source"" device to make it emit less unwanted noise.
  • studyres.com © 2026
  • DMCA
  • Privacy
  • Terms
  • Report