MAX114/MAX118 +5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1µA Power-Down _______________General Description
... Typical Operating Characteristics). A logic low on the PWRDN pin shuts the devices down, reducing supply current typically to 1µA when powered from a single +5V supply. A logic high on PWRDN wakes up the MAX114/MAX118, and the selected analog input enters the track mode. The signal is fully acquired ...
... Typical Operating Characteristics). A logic low on the PWRDN pin shuts the devices down, reducing supply current typically to 1µA when powered from a single +5V supply. A logic high on PWRDN wakes up the MAX114/MAX118, and the selected analog input enters the track mode. The signal is fully acquired ...
50-mA, 24-V, 3.2-μA Supply Current Low
... Low 3.2-μA Quiescent Current at 50 mA Stable With Any Capacitor ≥ 0.47 μF 50-mA Low-Dropout Regulator Available in 1.8 V, 1.9 V, 2.3 V, 2.5 V, 3 V, 3.3 V, 3.45 V, 5 V, and Adjustable (1.2 V to 15 V) Designed to Support MSP430 Families: – 1.9-V Version Ensured to be Higher Than Minimum VIN of 1.8 V – ...
... Low 3.2-μA Quiescent Current at 50 mA Stable With Any Capacitor ≥ 0.47 μF 50-mA Low-Dropout Regulator Available in 1.8 V, 1.9 V, 2.3 V, 2.5 V, 3 V, 3.3 V, 3.45 V, 5 V, and Adjustable (1.2 V to 15 V) Designed to Support MSP430 Families: – 1.9-V Version Ensured to be Higher Than Minimum VIN of 1.8 V – ...
MAX17497A/MAX17497B AC-DC and DC-DC Peak Current-Mode Converters with Integrated Step-Down Regulator General Description
... supports undervoltage lockout (UVLO) thresholds suitable to low-voltage DC-DC applications. Both devices also include a 3.3V fixed-output synchronous step-down regulator that delivers up to 600mA load current. The switching frequency of the MAX17497A flyback converter is 250kHz, while the MAX17497B ...
... supports undervoltage lockout (UVLO) thresholds suitable to low-voltage DC-DC applications. Both devices also include a 3.3V fixed-output synchronous step-down regulator that delivers up to 600mA load current. The switching frequency of the MAX17497A flyback converter is 250kHz, while the MAX17497B ...
74LCX162374 Low Voltage 16-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs
... The LCX162374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each byte ...
... The LCX162374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each byte ...
Medium Integrated Power Solution Using a Dual DC/DC Converter
... If 1.8-V LVCMOS is used, power rails up with the 1.8-V rails. If 3.3-V LVCMOS is used, power it up with the ANALOG33 rails (VDDA33_USB0/1). No specific voltage ramp rate is required for any of the supplies LVCMOS33 (USB0_VDDA33, USB1_VDDA33) if STATIC18 (USB0_VDDA18, USB1_VDDA18, DDR_DVDD18, SATA_VD ...
... If 1.8-V LVCMOS is used, power rails up with the 1.8-V rails. If 3.3-V LVCMOS is used, power it up with the ANALOG33 rails (VDDA33_USB0/1). No specific voltage ramp rate is required for any of the supplies LVCMOS33 (USB0_VDDA33, USB1_VDDA33) if STATIC18 (USB0_VDDA18, USB1_VDDA18, DDR_DVDD18, SATA_VD ...
PI6C5946002
... PCI-SIG jitter tool, which is regulated by US PCI-SIG organization. The jitter tool has PCIe Serdes embedded filter to calculate the equivalent jitter that relates to data link eye closure. Direct peak-peak jitter or phase jitter test data, normally is higher than jitter measure using PCI-SIG jitter ...
... PCI-SIG jitter tool, which is regulated by US PCI-SIG organization. The jitter tool has PCIe Serdes embedded filter to calculate the equivalent jitter that relates to data link eye closure. Direct peak-peak jitter or phase jitter test data, normally is higher than jitter measure using PCI-SIG jitter ...
MAX504/MAX515 5V, Low-Power, Voltage-Output, Serial 10-Bit DACs _______________General Description
... at REFOUT. The output stage can source and sink current so REFOUT can settle to the correct voltage quickly in response to code-dependent loading changes. Typically, source current is 5mA and sink current is 100µA. REFOUT connects the internal reference to the R-2R DAC ladder at REFIN. The R-2R ladd ...
... at REFOUT. The output stage can source and sink current so REFOUT can settle to the correct voltage quickly in response to code-dependent loading changes. Typically, source current is 5mA and sink current is 100µA. REFOUT connects the internal reference to the R-2R DAC ladder at REFIN. The R-2R ladd ...
AD8571
... combine low cost with high accuracy. (No external capacitors are required.) Using a patented spread-spectrum, auto-zero technique, the AD857x family eliminates the intermodulation effects from interaction of the chopping function with the signal frequency in ac applications. With an offset voltage o ...
... combine low cost with high accuracy. (No external capacitors are required.) Using a patented spread-spectrum, auto-zero technique, the AD857x family eliminates the intermodulation effects from interaction of the chopping function with the signal frequency in ac applications. With an offset voltage o ...
PI6C5946004
... PCI-SIG jitter tool, which is regulated by US PCI-SIG organization. The jitter tool has PCIe Serdes embedded filter to calculate the equivalent jitter that relates to data link eye closure. Direct peak-peak jitter or phase jitter test data, normally is higher than jitter measure using PCI-SIG jitter ...
... PCI-SIG jitter tool, which is regulated by US PCI-SIG organization. The jitter tool has PCIe Serdes embedded filter to calculate the equivalent jitter that relates to data link eye closure. Direct peak-peak jitter or phase jitter test data, normally is higher than jitter measure using PCI-SIG jitter ...
modified_version_3
... voltage pulse output, the rise time is ~10μs and the amplitude is more than 70kV with the highest repetition frequency up to 25Hz. The principle circuit is shown in Fig. 1, where C0, C1, C2 are energy storage capacitors, L is the charging inductance, MS1 and MS2 are magnetic switches, PT1 and PT2 ar ...
... voltage pulse output, the rise time is ~10μs and the amplitude is more than 70kV with the highest repetition frequency up to 25Hz. The principle circuit is shown in Fig. 1, where C0, C1, C2 are energy storage capacitors, L is the charging inductance, MS1 and MS2 are magnetic switches, PT1 and PT2 ar ...
JESD204B Survival Guide
... and evolved to meet the requirements necessary to transmit data. CML outputs are becoming more popular as the digital output interfaces in converters transition to serialized data transmission. However, CMOS and LVDS digital outputs are still being utilized today in current designs. There are applic ...
... and evolved to meet the requirements necessary to transmit data. CML outputs are becoming more popular as the digital output interfaces in converters transition to serialized data transmission. However, CMOS and LVDS digital outputs are still being utilized today in current designs. There are applic ...
In this section, we`ll introduce AC Analysis in Multisim. This is
... on the next page…yes there are a lot of fields which you can enter values in. We want to draw our attention to two in particular, however. At the top, is Voltage (Pk) field. This is the amplitude of the sine wave in Transient Analysis and the Interactive Simulation. Midway down the window there is a ...
... on the next page…yes there are a lot of fields which you can enter values in. We want to draw our attention to two in particular, however. At the top, is Voltage (Pk) field. This is the amplitude of the sine wave in Transient Analysis and the Interactive Simulation. Midway down the window there is a ...
MAX15058 Evaluation Kit Evaluates: General Description Features
... determine the value of the resistor-divider, first select R1 between 2kI and 10kI and then use the following equation to calculate R2: R2 = (VFB x R1)/(VOUT - VFB) where VFB is equal to the reference voltage at SS/REFIN and VOUT is the output. If no external reference is applied at SS/REFIN, the int ...
... determine the value of the resistor-divider, first select R1 between 2kI and 10kI and then use the following equation to calculate R2: R2 = (VFB x R1)/(VOUT - VFB) where VFB is equal to the reference voltage at SS/REFIN and VOUT is the output. If no external reference is applied at SS/REFIN, the int ...
MAX1272/MAX1273 Fault-Protected, 12-Bit ADCs with Software-Selectable Input Range General Description
... signal applied at the input channel. Use a low source impedance (<4Ω) to minimize gain error. The ADC’s small-signal input bandwidth depends on the selected input range and varies from 1.25MHz to 5MHz (see the Electrical Characteristics). The maximum sampling rate for the MAX1272/MAX1273 is 87ksps ( ...
... signal applied at the input channel. Use a low source impedance (<4Ω) to minimize gain error. The ADC’s small-signal input bandwidth depends on the selected input range and varies from 1.25MHz to 5MHz (see the Electrical Characteristics). The maximum sampling rate for the MAX1272/MAX1273 is 87ksps ( ...
A75D / A75DE SCR BATTERY CHARGER Digital METERS THREE
... A75DE - 100mv RMS, with or without battery connected, for a three phase unit Regulation +/- 0.5% from no load to full load over the specified input voltage, frequency and ambient temperature range. Audible Noise Less than 65dBA at any point 5 feet from any vertical surface of the battery charger. Lo ...
... A75DE - 100mv RMS, with or without battery connected, for a three phase unit Regulation +/- 0.5% from no load to full load over the specified input voltage, frequency and ambient temperature range. Audible Noise Less than 65dBA at any point 5 feet from any vertical surface of the battery charger. Lo ...
Atmel LED Driver-MSLB9061 LED Driver Module Datasheet
... Note 1. Full power available with PWR input voltage greater than 6.5V. For 3.1V to 3.6V operation, doubling charge pump(U2) and C12, C13 are required. Note 2. Minimum SCL clock frequency is limited by the bus timeout feature, which resets the serial bus interface if either SDA or SCL is held low f ...
... Note 1. Full power available with PWR input voltage greater than 6.5V. For 3.1V to 3.6V operation, doubling charge pump(U2) and C12, C13 are required. Note 2. Minimum SCL clock frequency is limited by the bus timeout feature, which resets the serial bus interface if either SDA or SCL is held low f ...
BD8151EFV,BD8157EFV : Power Management ICs
... However, 10 µs is the rough calculation value of the DC/DC response speed. Please set the capacitance considering the sufficient margin so that these two values are within the standard value range. (3) Selecting the input capacitor Since the peak current flows between the input and output at the DC/ ...
... However, 10 µs is the rough calculation value of the DC/DC response speed. Please set the capacitance considering the sufficient margin so that these two values are within the standard value range. (3) Selecting the input capacitor Since the peak current flows between the input and output at the DC/ ...
Simulation and fabrication of single phase Z-Source inverter for resistive load Meera Murali, Prathamesh Deshpande, Burhanuddin Virpurwala, Piyusha Bhavsar
... efficiency, reliability, etc. In an attempt to overcome these disadvantages, from the year 2002 a new concept was introduced which combines the effects of both voltage source and current source. The basic concept of impedance network was developed by Fang Z. Peng in 2002, [1]. In his paper, he prese ...
... efficiency, reliability, etc. In an attempt to overcome these disadvantages, from the year 2002 a new concept was introduced which combines the effects of both voltage source and current source. The basic concept of impedance network was developed by Fang Z. Peng in 2002, [1]. In his paper, he prese ...
exp04
... input (+) goes more positive than the inverting (-) input, and vice versa. The symbols + and – do not mean that that you have to keep one positive with respect to the other; they tell you the relative phase of the output. (Vin=V1-V2) A fraction of a millivolt between the input terminals will swing ...
... input (+) goes more positive than the inverting (-) input, and vice versa. The symbols + and – do not mean that that you have to keep one positive with respect to the other; they tell you the relative phase of the output. (Vin=V1-V2) A fraction of a millivolt between the input terminals will swing ...
Chapter 4.9 - Automotive Electronic Circuits
... and DMOS power FETs. All inputs are CMOS compatible. Each independent output is internally clamped to 65 V, current limited to 3.0 A, and has an rDS(on) of 0.25 Ω with VPWR 9.0 V and may be paralleled to lower rDS(on). Fault output reports existence of open loads (outputs “On” or “Off”), ...
... and DMOS power FETs. All inputs are CMOS compatible. Each independent output is internally clamped to 65 V, current limited to 3.0 A, and has an rDS(on) of 0.25 Ω with VPWR 9.0 V and may be paralleled to lower rDS(on). Fault output reports existence of open loads (outputs “On” or “Off”), ...
GAL26CV12
... Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, t ...
... Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, t ...
Integrating ADC
An integrating ADC is a type of analog-to-digital converter that converts an unknown input voltage into a digital representation through the use of an integrator. In its most basic implementation, the unknown input voltage is applied to the input of the integrator and allowed to ramp for a fixed time period (the run-up period). Then a known reference voltage of opposite polarity is applied to the integrator and is allowed to ramp until the integrator output returns to zero (the run-down period). The input voltage is computed as a function of the reference voltage, the constant run-up time period, and the measured run-down time period. The run-down time measurement is usually made in units of the converter's clock, so longer integration times allow for higher resolutions. Likewise, the speed of the converter can be improved by sacrificing resolution.Converters of this type can achieve high resolution, but often do so at the expense of speed. For this reason, these converters are not found in audio or signal processing applications. Their use is typically limited to digital voltmeters and other instruments requiring highly accurate measurements.