ADN4666 数据手册DataSheet 下载
... Active High Enable and Power-Down Input (3 V TTL/CMOS). When EN is low and EN is high, the receiver outputs are disabled and are in a high impedance state. When EN is high and EN is low or when EN is low and EN is low, the receiver outputs are enabled. When EN is high and EN is high, the receiver ou ...
... Active High Enable and Power-Down Input (3 V TTL/CMOS). When EN is low and EN is high, the receiver outputs are disabled and are in a high impedance state. When EN is high and EN is low or when EN is low and EN is low, the receiver outputs are enabled. When EN is high and EN is high, the receiver ou ...
Ultra-Low Noise Amplifier
... The COMLINEAR CLC1002(single) is a high-performance, voltage feedback amplifier with ultra-low input voltage noise, 0.6nV/√Hz. The CLC1002 provides 965MHz gain bandwidth product and 170V/μs slew rate making it well suited for high-speed data acquisition systems requiring high levels of sensitivity a ...
... The COMLINEAR CLC1002(single) is a high-performance, voltage feedback amplifier with ultra-low input voltage noise, 0.6nV/√Hz. The CLC1002 provides 965MHz gain bandwidth product and 170V/μs slew rate making it well suited for high-speed data acquisition systems requiring high levels of sensitivity a ...
Opti Information
... When engine speed is below 1,500 RPM, a code 41 sets if there is an open in the ignition control line (or if the ignition control line is shorted to voltage that is higher than 4.5 Volts) Code 41 also sets if there is also an open terminal in the ignition control line. Code 41 sets if there is a ...
... When engine speed is below 1,500 RPM, a code 41 sets if there is an open in the ignition control line (or if the ignition control line is shorted to voltage that is higher than 4.5 Volts) Code 41 also sets if there is also an open terminal in the ignition control line. Code 41 sets if there is a ...
J. Hu, A.D. Sagneri, J.M. Rivas, Y. Han, S.M. Davis, and D.J. Perreault, “High-Frequency Resonant SEPIC Converter with Wide Input and Output Voltage Ranges, 2008 IEEE Power Electronics Specialists Conference , June 2008, pp. 1397 – 1406
... and control method suitable for high frequency (HF) and very high frequency (VHF) dc-dc power conversion. The proposed design features high efficiency over a wide input and output voltage range, up-and-down voltage conversion, small size, and excellent transient performance. In addition, a resonant g ...
... and control method suitable for high frequency (HF) and very high frequency (VHF) dc-dc power conversion. The proposed design features high efficiency over a wide input and output voltage range, up-and-down voltage conversion, small size, and excellent transient performance. In addition, a resonant g ...
EE 174 Spring 2016
... Vdc1 and Vdc2 are dc voltages and RS represents the source resistance. Vio is the difference of Vdc1 and Vdc2. It may be positive or negative. For a 741C OPAMP the maximum value of Vio is 6mV. It means a voltage ± 6 mV is required to one of the input to reduce the output offset voltage to zero. The ...
... Vdc1 and Vdc2 are dc voltages and RS represents the source resistance. Vio is the difference of Vdc1 and Vdc2. It may be positive or negative. For a 741C OPAMP the maximum value of Vio is 6mV. It means a voltage ± 6 mV is required to one of the input to reduce the output offset voltage to zero. The ...
ICS9DB202.pdf
... In these systems, a jitter-attenuating device may be necessary in order to reduce high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS9DB202 has two PLL bandwidth modes. In low bandwidth mode, the PLL loop bandwidth is 500kHz. This set ...
... In these systems, a jitter-attenuating device may be necessary in order to reduce high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS9DB202 has two PLL bandwidth modes. In low bandwidth mode, the PLL loop bandwidth is 500kHz. This set ...
78Q8392L/A03 Low Power Ethernet Coaxial Transceiver
... Noise on the transmission media is rejected by the receiver squelch circuitry, which determines valid data via three criteria: Average DC level, pulse width and transition period. The DC voltage level is detected and compared to a set level in the receiver comparator circuit. The pulse width must be ...
... Noise on the transmission media is rejected by the receiver squelch circuitry, which determines valid data via three criteria: Average DC level, pulse width and transition period. The DC voltage level is detected and compared to a set level in the receiver comparator circuit. The pulse width must be ...
MAX1146–MAX1149 Multichannel, True-Differential, Serial, 14-Bit ADCs General Description
... The MAX1146/MAX1148 operate from a single +4.75V to +5.25V supply, and the MAX1147/MAX1149 operate from a single +2.7V to +3.6V supply. All analog inputs are software configurable for unipolar/bipolar and single-ended/differential operation. The 4-wire serial interface connects directly to SPI™/QSPI ...
... The MAX1146/MAX1148 operate from a single +4.75V to +5.25V supply, and the MAX1147/MAX1149 operate from a single +2.7V to +3.6V supply. All analog inputs are software configurable for unipolar/bipolar and single-ended/differential operation. The 4-wire serial interface connects directly to SPI™/QSPI ...
ACTIONI/Q Q498 ® DC Powered DC Input Field Configurable
... describes a few process control applications and how to configure the unit in order to perform the various operations. Track & Hold The Digital Input is used as the control element for Track & Hold. Short the Digital Input (Pin A6) to Digital Common (Pin A3) using an external relay or switch. The An ...
... describes a few process control applications and how to configure the unit in order to perform the various operations. Track & Hold The Digital Input is used as the control element for Track & Hold. Short the Digital Input (Pin A6) to Digital Common (Pin A3) using an external relay or switch. The An ...
Lab 4 – Intro to Digital Logic and Transistors
... 2. Build logic gates using pushbuttons Logic gates are the basic building blocks of all digital electronics. Logic gates have some number of binary inputs, usually two, and one output. You will now build two basic logic gates, the AND gate and the OR gate, using pushbuttons. The symbol and truth tab ...
... 2. Build logic gates using pushbuttons Logic gates are the basic building blocks of all digital electronics. Logic gates have some number of binary inputs, usually two, and one output. You will now build two basic logic gates, the AND gate and the OR gate, using pushbuttons. The symbol and truth tab ...
Logic Switches Operating at the Minimum Energy of Computing
... The bit rate for the tests has been chosen low enough to not have issues with the propagation delay. This means that delays on the two different signal paths can be neglected with respect the bit duration. Moreover the expected delay introduced by the under-powered gate will be much bigger than the ...
... The bit rate for the tests has been chosen low enough to not have issues with the propagation delay. This means that delays on the two different signal paths can be neglected with respect the bit duration. Moreover the expected delay introduced by the under-powered gate will be much bigger than the ...
AN-1687 LM20125 Evaluation Board (Rev. A)
... during startup, and if RF is too large the resulting voltage drop can trigger the UVLO comparator. For the demo board, a 1Ω resistor is used for RF ensuring that UVLO will not be triggered after the part is enabled. A recommended 1 µF CF capacitor coupled with the 1 Ω resistor provides roughly 16dB ...
... during startup, and if RF is too large the resulting voltage drop can trigger the UVLO comparator. For the demo board, a 1Ω resistor is used for RF ensuring that UVLO will not be triggered after the part is enabled. A recommended 1 µF CF capacitor coupled with the 1 Ω resistor provides roughly 16dB ...
HMC543LC4B 数据资料DataSheet下载
... The HMC543LC4B is a 4-bit digital phase shifter which is rated from 8 to 12 GHz, providing 0 to 360 degrees of phase coverage, with a LSB of 22.5 degrees. The HMC543LC4B features very low RMS phase error of 5 degrees and extremely low insertion loss variation of ±0.8 dB across all phase states. This ...
... The HMC543LC4B is a 4-bit digital phase shifter which is rated from 8 to 12 GHz, providing 0 to 360 degrees of phase coverage, with a LSB of 22.5 degrees. The HMC543LC4B features very low RMS phase error of 5 degrees and extremely low insertion loss variation of ±0.8 dB across all phase states. This ...
2.5 A high-side driver industrial intelligent power switch
... deactivates itself. The following actions are taken: all the output stage is switched off; the signal DIAG2 is activated (active low). Normal operation is resumed as soon as (typically after some seconds) the chip temperature monitored goes back below Θlim-ΘH. The different thresholds with hystereti ...
... deactivates itself. The following actions are taken: all the output stage is switched off; the signal DIAG2 is activated (active low). Normal operation is resumed as soon as (typically after some seconds) the chip temperature monitored goes back below Θlim-ΘH. The different thresholds with hystereti ...
DAC813 数据资料 dataSheet 下载
... Linearity error as used in D/A converter specifications by Burr-Brown is the deviation of the analog output from a straight line drawn between the end points (inputs all “1s” and all “0s”). The DAC813 linearity error is specified at ±1/4LSB (max) at +25°C K grades, and ±1/2LSB (max) for J grades. ...
... Linearity error as used in D/A converter specifications by Burr-Brown is the deviation of the analog output from a straight line drawn between the end points (inputs all “1s” and all “0s”). The DAC813 linearity error is specified at ±1/4LSB (max) at +25°C K grades, and ±1/2LSB (max) for J grades. ...
The CCB external hardware interfaces
... change, can be accommodated by the CCB logic, any jitter and thermal drifts in these ...
... change, can be accommodated by the CCB logic, any jitter and thermal drifts in these ...
High Voltage, Precision Difference Amplifier AD8209
... resistor network attenuates the common-mode signal by a ratio of 1/14. The A1 amplifier inputs are held within the power supply range, even as Pin 1 and Pin 8 exceed the supply or fall below the common (ground). A reference voltage of 350 mV biases the attenuator above ground, allowing Amplifier A1 ...
... resistor network attenuates the common-mode signal by a ratio of 1/14. The A1 amplifier inputs are held within the power supply range, even as Pin 1 and Pin 8 exceed the supply or fall below the common (ground). A reference voltage of 350 mV biases the attenuator above ground, allowing Amplifier A1 ...
Analog-to-digital converter
An analog-to-digital converter (ADC, A/D, or A to D) is a device that converts a continuous physical quantity (usually voltage) to a digital number that represents the quantity's amplitude.The conversion involves quantization of the input, so it necessarily introduces a small amount of error. Furthermore, instead of continuously performing the conversion, an ADC does the conversion periodically, sampling the input. The result is a sequence of digital values that have been converted from a continuous-time and continuous-amplitude analog signal to a discrete-time and discrete-amplitude digital signal.An ADC is defined by its bandwidth (the range of frequencies it can measure) and its signal to noise ratio (how accurately it can measure a signal relative to the noise it introduces). The actual bandwidth of an ADC is characterized primarily by its sampling rate, and to a lesser extent by how it handles errors such as aliasing. The dynamic range of an ADC is influenced by many factors, including the resolution (the number of output levels it can quantize a signal to), linearity and accuracy (how well the quantization levels match the true analog signal) and jitter (small timing errors that introduce additional noise). The dynamic range of an ADC is often summarized in terms of its effective number of bits (ENOB), the number of bits of each measure it returns that are on average not noise. An ideal ADC has an ENOB equal to its resolution. ADCs are chosen to match the bandwidth and required signal to noise ratio of the signal to be quantized. If an ADC operates at a sampling rate greater than twice the bandwidth of the signal, then perfect reconstruction is possible given an ideal ADC and neglecting quantization error. The presence of quantization error limits the dynamic range of even an ideal ADC, however, if the dynamic range of the ADC exceeds that of the input signal, its effects may be neglected resulting in an essentially perfect digital representation of the input signal.An ADC may also provide an isolated measurement such as an electronic device that converts an input analog voltage or current to a digital number proportional to the magnitude of the voltage or current. However, some non-electronic or only partially electronic devices, such as rotary encoders, can also be considered ADCs. The digital output may use different coding schemes. Typically the digital output will be a two's complement binary number that is proportional to the input, but there are other possibilities. An encoder, for example, might output a Gray code.The inverse operation is performed by a digital-to-analog converter (DAC).