Download AN-566: A Geophone/Hydrophone Acquisition Reference Design

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AN-566 Preliminary Technical Data
TECHNICAL NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • 781/329-4700 • World Wide Web Site: http://www.analog.com
A Geophone/Hydrophone acquisition reference design based on the
AD1555/AD1556 chipset
by Alain Guery
INTRODUCTION
This application note describes a reference design based on the
24 Bit sigma-delta high dynamic range AD1555/AD1556 chipset. This chip-set allows direct acquisition of high dynamic
sensors like geophones or hydrophones. Acquisition of other
high dynamic range low frequency range ( up to few kHz )
sensors can also be done.
0.9" (23 m m )
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The intent of this note is to provide the detailed description of
this design. These guidelines can be used to ease the design
using the AD1555/AD1556 chip-set. The main goal of this
design is to give a baseline design that can be customized at
user convenience rather than a design which covers all acquisition needs.
Figure 1. Implementation of the reference design.
This design is very dense ( less than 1 inch by 2 inches per
channel ), can be easily extended to do a multichannel acquisition system, and demonstrates the specific high accuracy
performances of the chip-set. Performance of 120dB dynamic
range in 408Hz bandwidth, equivalent input noise of 80nVrms
in 101 Hz bandwidth and distortion of -120 dB with a total
power dissipation lower than 90mW per channel typically can
be achieved.
GENERAL DISCUSSION
The implementation of this one channel acquisition AD1555/
AD1556 reference design occupies less than one 1 inch by 2
inches per channel on a one side board and is shown in figure
1. In multichannel applications, some components can be
shared to further reduce the estate per channel. This reference
design incliudes many functionalities like EMI/RFI filtering,
lightning protection, sensor and acquisition system build-in
testability, calibration, reference voltage and easy to use serial
digital interface. The schematic of the reference design is
shown in figure 2.
The AD1555 is a complete sigma-delta modulator, combined
with a programmable gain amplifier intended for low frequency, high dynamic range measurement applications. The
AD1555 outputs a ones-density bit stream proportional to the
analog input. When used in conjunction with the AD1556
digital filter/decimator, a high performance ADC is realized.
Input Filtering
Some filtering of the input signal coming from the sensor is
usually required before acquisition. Depending on the application, the requirements of this filter can vary among EMI/RFI
filtering to prevent high frequency noise coming in and being
detected by the acquisition system, common mode filtering and
polarization when the sensor is floating, lightning protection
when sensors such as geophone are connected through long
cables and are exposed to the elements. It is difficult to cover
all the specific requirements of each application with the same
filter. The filter implemented in the reference design answers
some of these requirements and can be customized according
to each specific application.
A full description of the AD1555/AD1556 is available in the
AD1555/AD1556 data sheet and should be consulted when
utilizing this application note. The data sheet provides detailed
information on the functionality of the AD1555/AD1556 chipset and will be referenced often in this application note.
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PIN4
PIN40
PIN2
SENSOR-
CGND
SENSOR+
PIN36
PIN37
PIN38
PIN17
PIN3
PIN5
PIN8
49.9
R6
49.9
AGND
1
A0
R5
16
AGND
A1
AGND
TEST-
CAL-
CAL+
10K
R2
10
11
4.7nF
C14
4.7nF
C13
A0
A1
49.9
R4
49.9
R3
ADG609BRU
DB
9
S4B
S3B
13
S1B
12
S2B
10K
R1
4
5
6
7
C12
GND
-VA
EN
+VA
12nF
S1A
S2A
S3A
S4A
DA
8
6
5
8
7
U4
14
AIN-
AIN+
TIN-
TIN+
AGND
15
3
2
+VA
C16
0.1uF
-VA
C18
0.1uF
VL
8
3
7
C9
0.1uF
10
2.5/3.0
TEMP
NC
TRIM
VOUT
NC
AGND
C3
0.1uF
AD780BR
+VA
2
+VIN
GND
PIN9
+VA
-VA
AD1555BP
R7
C11
22uF
0.0
+
MODIN
PG AOUT
NC
REFCAP2
REFCAP1
28
2
9
24
23
5
6
1
+VA
U5
AGND
MCLK
MDATA
MFLG
CB4
CB3
CB2
CB1
CB0
U1
AGND
18
17
15
14
13
12
11
C15
0.1uF
1
5
+VA
S1
U3
IN
DGND
S2
ADG719BRT
D
VL
6
4
PIN21
MDATA
AGND
22uF
+ C1
PIN15
C17
0.1uF
C2
0.1uF
-VA
33
21
10
9
8
7
6
5
4
3
2
35
36
38
39
40
41
42
43
C4
0.1uF
-VA
CS
NC
NC
H/S
BW2
BW1
AD1556AS
NC
NC
NC
NC
CLKIN
BW0
SYNC
PGA3
PWRDN
RESET
PGA2
PGA4
ERROR
DRDY
DOUT
PGA1
PGA0
MCLK
DIN
SCLK
MFLG
MDATA
TDATA
CSEL
RSEL
R/W
U2
C7
0.1uF
CB4
CB3
CB2
CB1
CB0
22uF
C10
PIN16
VL
11
44
22
VL
VL
VL
26
3
4
20
21
25
19
+VA
+VA
-VA
-VA
-VA
REFIN
VL
AGND3
AGND2
AGND1
DG ND
22
27
1
16
2
VDD
GND
3
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DG ND
DG ND
DG ND
DG ND
4
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12
34
23
24
TEST+
+
PIN1
16
CS
TDATA
SCLK
DIN
DOUT
DRDY
ERROR
RESET
SYNC
PWRDN
CLKIN
30
13
19
14
15
20
25
31
26
37
27
28
1
DGND
CSEL
29
32
RSEL
R/W
C8
0.1uF
18
17
DGND
C6
0.1uF
+
PIN39
PIN35
PIN33
PIN19
PIN32
PIN34
PIN18
PIN22
PIN23
PIN24
PIN25
PIN28
PIN20
PIN26
PIN27
PIN31
22uF
C5
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Figure 2. Schematic.
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The filter implemented on the reference design consists of a
low pass common mode filter made by R5, C13, C14 and R6
followed by a differential mode low pass filter made by R3,
C12 and R4. The cutoff frequency of the differential filter is set
below the sampling frequency of the sigma-delta modulator of
the AD1555 and therefore this filter can served as the antialiaising filtering. Because of the architecture of the AD1555,
there is usually no need for another anti-aliaising filter. The
common mode and differential filter cut off frequencies on the
reference design are set respectively at 675 kHz and 66kHz.
The differential filter cutoff frequency is chosen deliberately
significantly lower than the common mode filter cutoff frequency to remove differential signals generated by any
mismatch which could be present in the common mode filter.
The serial resistors R3, R4, R5 and R6 must be kept low to
reduce their noise contribution which could reduce the dynamic range mainly at the highest gain settings. With the
values chosen in the reference design, the dynamic range loss
⌬dynamic is close to 0.2dB for the gain setting of 34 at the sampling rate of 4ms (250 Hz).
nADC is the equivalent input noise of the AD1555.
nADC is 80nVrms for the gain setting of 34 at F0 = 250Hz (see
Table I of the data sheet).
nR is the thermal noise of the serial resistors :
nR2 Ⲙ 4kT.4.R.(BW-3dB)
R = R3 = R4 = R5 = R6
BW-3dB is a good approximation of the noise bandwidth due to
the steep digital filter response (see Table II of the data sheet).
Note that C12, C13 and C14 are on the signal path and, therefore, should have a very good linearity as an NPO ceramic
capacitor or a polypropylene type.
If desired, the cutoff frequencies can be lowered by increasing
the serial resistors or the capacitors which will result in a tradeoff between the dynamic range loss at high gain and the size of
the capacitors.
Lightning protection
The reference design is designed to handle severe stresses
which could likely happen because it is directly connected to
remote sensors. For instance, in seismic land based systems
where geophones are used, lightning could eventually propagate through the geophone cable to the acquisition system. The
voltage spikes induced by lightning is first clamped by the
surface mount dual gas arrestor Z1 from Joslyn, part number
2036-90-A, to about 100V. The signals on AD1555 AIN inputs are also clamped to the analog supply rails +VA and -VA by
robust clamping diodes integrated in the AD1555. Thus, the
serial resistors R3, R4, R5 and R6 limit the pulsed current
which flows in the AIN inputs to about 1A. The AD1555 AIN
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Calibration process
The AD1555 is intended to be used with a calibration process
to achieve high precision absolute accuracies. This calibration
process can be done easily by acquiring ground and full-scale
references for each gain setting.
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⌬dynamic Ⲙ 20.LOG10[((nR2 + nADC2)1/2/nADC]
Where :
inputs are designed to handle 1.5A pulsed current during 2␮s
without experiencing any destructive damage or latch-up
whether the AD1555 is powered on or off. Meanwhile, enough
time should be left between each spike to avoid excessive
power dissipation. When the stress pulses are longer than 2␮s,
the current limitation should be reduced by increasing the
values of R3, R4, R5 or R6. The power supplies +VA and -VA
should be able to handle a high pulsed current which returns
through them. A tranzorb on each supply, common to all channels in a multichannel configuration, could be enough to
achieve the desired protection. Meanwhile, the power supply
design should take in consideration this requirement.
The offset for each gain setting can be known by using the
AD1555 internal multiplexer in the mode “ Ground input”
which shorts the inputs to ground. It is recommended to calibrate the offset for each gain setting due to potential offset
mismatch. Then, each gain setting can be calibrated accurately
by applying known voltage references close to full-scale between CAL+ and CAL- inputs of the module. When the
channel S1 of the multiplexer U4 is selected and the AD1555
internal multiplexer uses the mode “Test input”, these reference voltages can be measured through the AD1555 with the
corresponding gain setting. Use of the lowest bandwidth (F0 =
250Hz) filter of the AD1556 and averaging will reduce the
noise of the calibration measurements. The high input impedance of the AD1555, 140M⍀ typical, minimizes errors due to
source impedance of the reference voltages which can be generated directly from a precision resistive network.
Moreover, although gain and offset temperature drift of the
AD1555 are low, the calibration accuracy over temperature can
be further improved by monitoring the ambient temperature.
The reference design offers a cheap way to do that using the
AD780 Temperature output pin ( TEMP ) feature. The voltage of the temperature pin TEMP of the AD780 is
proportional to the absolute temperature with a temperature
sensitivity of +1.9mV/oC typical. By acquiring this temperature
dependant voltage through the channel S4 of the multiplexer
U4, temperature change can be detected and the user can
decide to launch a new calibration process at the actual ambient temperature.
Only one calibration circuitry consisting of the reference voltages and the multiplexer U4 can be used for all channels in
multichannel system.
Self-test circuitry
The AD1555/AD1556 reference circuit is designed to ease the
testability of both the acquisition system and the sensor. As
described in chapter Programming the AD1555 of the data
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sheet, a signal on TIN inputs can be applied on the sensor
through the AD1555 internal multiplexer and the sensor response can be measured simultaneously with the AD1555.
TEST+
For instance, that allows the measurement of the impedance of
the sensor and its cable which helps to localize any potential
failures ( open or short-circuit ). A voltage source applied between TEST+ and TEST- will force, through the 10k⍀
resistors R1 and R2, a current into the sensor when the multiplexer U4 is on channel S3 and the internal multiplexer of the
AD1555 on “ Sensor Test1” configuration. The figure 3 shows
a simplified schematic of this configuration.
T E ST +
Ro n U4
z 30 8
S en sor+
R5
49.9 8
R6
S en sor- 49.9 8
Ro n U4
T E ST -
z 30 8
10k 8
R2
10k 8
R3
49.9 8
R6
R4
Sensor-
49.9 8
49.9 8
Ron U4
Tin+
z 66 8
Ain+
Ain-
z 166 8
R2
10k 8
Tin-
AD1555
Figure 4. Sensor leakage measurement schematic.
Like the sensor, the acquisition system can be also verified
easily.
Noise level and dynamic range performance can be checked
using the AD1555 internal multiplexer in “Ground input”
configuration. In this mode, the AD1555 PGA inputs are
shorted by an internal accurate 1k⍀ resistor. Noise level and
dynamic range can be checked for each gain setting with the
expected values defined in table I of the data sheet. The values
in this table do not include the noise of the internal 1 k⍀ resistor and should be added as follows :
z 66 8
Ain +
z 66 8
R4
49.9 8
R5
49.9 8
z 30 8
z 166 8
R1
10k 8
ZL
TEST-
T in +
R3
49.9 8
Sensor+
z 166 8
R1
Ron U4
z 30 8
Ain -
z 166 8
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T in -
AD 1 555
Figure 3. Sensor impedance measurement schematic.
nT Ⲙ (nADC2 + 16.10-18.BW-3dB)1/2
The accuracy of the measurement is slightly affected by the
serial resistance of the AD1555 inputs and the on resistance of
the multiplexer U4. By using the typical values shown on figure
2, impedance measurement accuracy of a few percent is possible. To further improve this accuracy, these serial resistances
which can deviate at ambient temperature by +/-20% from the
typical value, can be determined in factory by measuring
known impedances in place of the sensor. The remaining error
due to these serial resistances is their temperature variation
which can vary by +/-20% over -55oC to +85oC temperature
range. Notice that this measurement can be either done with
DC or with a low frequency source. With the multiplexer U4
on channel S2 and the internal AD1555 multiplexer on “Test
input”, the amplitude of the source applied to the inputs of the
module can be measured accurately and therefore doesn’t
affect the impedance measurement accuracy.
Where :
nT is the expected equivalent input noise in “Ground input”
configuration.
nADC is the equivalent input noise of the AD1555. It is given in
table I.
BW-3dB is a good approximation of the noise bandwidth due to
the steep digital filter response (see Table II of the data sheet).
Similarly, performance of the acquisition system in the presence of signal like linearity and intermodulation or impulse
response can be verified by applying an AC or two tone reference source between either TEST+ and TEST- or CAL+ and
CAL- inputs.
The impedance between the sensor and the ground which
allows the detection of leak and isolation issues in the sensor
cable can be done by a similar manner. By selecting the
AD1555 internal multiplexer in “Sensor Test2” configuration
which forces the source signal on only one side of the sensor,
isolation impedance between the sensor and the ground is
measured. Figure 4 shows a simplified schematic of this configuration. The low side input of the AD1555 is always at the
same voltage ( TEST-) while a possible leakage impedance ZL
on the sensor forms a voltage divider with resistor R1 and the
other serial resistors. The output, AIN+, will depend on the
leakage impedance ZL. When ZL is high, the AIN+ voltage is
close to the TIN+ voltage.
AD1555 circuit
The AD1555 is a fully integrated acquisition solution which
requires only few external passive devices.
The PGA output PGAOUT is usually connected to the modulator input MODIN by a short-circuit (resistor R7). If desired,
this resistor R7 can be used to slightly change the voltage
ranges. In fact, the AD1555 PGA still behaves well with output
range up to +/-3.5V. Resistor R7 and the input impedance of
the modulator, 20k⍀ typical, will reduce this swing to get the
modulator range of +/-2.25V. Also R7 can be replaced by a
capacitor to have a high pass filter.
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AN-566 Preliminary Technical Data
Power supply
The reference design is intended to be used with separate digital and analog supplies : a dual analog supply +/-5V (+VA,
-VA) and a +5V digital supply. The necessary decoupling components are on board. There is no connection between the
analog and digital ground planes on the reference design board
and, thus, this connection can be made at an optimal location
in the system. This optimal location depends a lot on the system architecture and is usually determined by experiment. It
was found that a short connection between pin 38 ( AGND )
and pin 35 ( DGND ) is a good location when the reference
design is used in a stand alone application.
Figure 5. Top Layer ( Not to scale ).
This design can be used also with a 3V digital supply with the
following modifications :
- The AD1555 digital supply (pin 19) is connected through a
15⍀ resistor to the +5V analog supply +VA. Thus, the
AD1555 remains supplied with 5V without any need of an
additional supply.
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- 10k⍀ resistors should be inserted on MDATA and MFLG
lines between the AD1555 and the AD1556 to protect the
AD1556 against the AD1555 5V logic. The delay introduced
by the time constant of the 10k⍀ resistor and the AD1556
input capacitance is compatible with the AD1556 timing.
Figure 6. Shield Layer ( Not to scale ).
The AD1555 and the AD1556 can be shutdown by bringing
PWRDN high (pin 19) or by using the software programmable
AD1556 configuration register. Also, the shutdown consumption of the AD1555 is slightly lower when MCLK is low. To
take benefit of this additional power saving, a switch U3 can be
added. The switch U3 forces MCLK low when PWRDN is
high.
Implementation and Layout
The reference design is implemented on a 4 layer board:
- The top layer is shown in figure 5.
Figure 7. Ground Layer ( Not to scale ).
- The layer below called “shield” is shown in figure 6.
- The next layer is used for both digital and analog ground
planes and shown in figure 7.
- The fourth layer is shown in figure 8.
One of the most critical line is the return ground connection of
the pin AGND3 of the AD1555 ( pin 22 ). From this pin, it is
routed first to the low side of the reference decoupling capacitor C11, then to the reference voltage ground (pin 4) and
finally returns to the analog ground plane at the pin AGND1 of
the AD1555 (pin 1).
Figure 8. Bottom Layer ( Not to scale ).
The bill of material is listed in Table I.
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Table I. Bill of material.
Integrated Circuits
U1
U2
U3
U4
U5
AD1555BP.
AD1556AS.
switch ADG719BRT.
multiplexer ADG609BRU.
reference AD780BR.
Capacitors
C2-C4,C6-C9,C15-C18
C1,C5,C10,C11
C12
C13,C14
100nF X7R Ceramic
22␮F 6.3V Tantalum B size
12nF NPO 50V 1210 size Ceramic
4.7nF NPO 100V 1206 size Ceramic
Kemet T494B226K006
Kemet C1210C123K5G
Kemet C1206C472K5G
Resistors
R1,R2
R3-R6
10k⍀ Resistor.
49.9⍀ Resistor.
Protection
Z1
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gas discharge tube Joslyn 2036-90-A
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