Download CMP Modeling - University of Utah

Lecture 7.0
Device Physics
Electronic Devices

Passive
 Active
Components
Components
 Resistance (real #)  Reactance
(Imaginary #)
– Conductor
– Resistor
– Battery
–
–
–
–
–
Capacitor
Inductor
Diode
Transistor
Surge Protector
Conductors

Materials
– Metal Interconnects
• Wire Lines
– W, Al, Cu
• Vias
–W
– Gates
•W
Resistance,
R=  L/A
Capacitance
C=oA/d
Metal Junctions

Metal Interconnects
• Wire Lines
– W, Al, Cu
• Vias
–W
– Gates
•W
Equilibration of Ef
Difference in Work Functions
Resistors

On Chip
– Low resistance
• Silicon with dopants at a particular
concentration
– High resistance
• Insulator with a specific size
– Gate oxide-tunneling junction
– Oxide Insulator between two conductors

Circuit Board Resistors
Capacitance
C=oA/d
=C/Co
=1+e
e =
electric
susceptibility
Capacitor





Allows AC signal
to pass
Stops DC part of
signal
Slow build-up of
charge
Timing Circuits
Signal Integration

Reactance
 Imaginary # for
Resistance
Capacitors in Silicon Chips

On chip
– SiO2
– Si3N4
 On Circuit Board
– BaTiO3
– (Pb,La)TiO3

Materials
– SiO2
– Si3N4
– BaTiO3
– (Pb,La)TiO3
Dielectric Constant

opt= (V/C)2
opt= n2
n=Refractive index
Circuit Board Capacitor
Ni Electrodes
BaTiO3 Dielectric = 2000-3000
On Chip Capacitor (Memory Chip)

An electric circuit element used to temporarily
STORE a charge, consisting of TWO
CONDUCTIVE plates separated and insulated
from each other by a DIELECTRIC.
Void
Wet Gate Ox
Dielectric Cell Nitride
Container Cell - Combo Poly
17 Masking Level
Native Oxide
Top Cell Plate - Insitu Poly3
(52 Masking Level)
Inductor

What is it?
– Coil of wire
Not used on Chip
 On Circuit Board

– Used often

Reactance
– (imaginary # for
resistance)
P-n junction

One way flow of current
– Diode bridge
• Converts AC to DC

Photo Diode Laser
P-N Junction - Diode

N-type
P-type
Ef
Ef
Diodes

P-n junction

One way flow of
current
– Diode bridge
• Converts AC to DC

Photo Diode Laser
Poisson’s Equation
 2U = -/( o
• N side
)
–n= - e Nd
• P side
–p=+ e Na
• U=Φ = Potential (volt)
Poisson Eq. d2U/dx2 = -/(o)
n p   g ( E ) f ( E )dE
f ( E )  exp[( E f  E ) / k BT ]
g ( E )  Ce [ E  ( E g  e )]1/ 2
n p  N c exp[( E f  E g  e ) k BT ]
nn  N c exp[( E f  E g ) k BT ]
pn  N v exp[(  E f ) k BT ]
p p  N v exp[(  e  E f ) k BT ]
 [
N N
k BT
] ln[ a 2 d ]
e
ni
P-N Junction (Diode) – no bias V

Thickness of depletion layers
– Nd ln = Np lp

Current to equilibrate electrons from
p zone to n zone due to competition
of diffusion vs drift due to contact Ф.
I diffusion  I drift   n p
I drift  I o  C exp[( E f  Eg  e ) / k BT ]
Diode with Applied Voltage
I
- Io
Reverse Bias
V
Forward Bias
P-N Junction (Diode) – with forward bias V

Current to equilibrated electrons
from p zone to n zone.
I diffusion  C exp[( E f  Eg  e  eV ) / k BT ]
I  I diffusion  I drift  I o exp( eV / k BT )  1
P-N Junction (Diode) – with reverse bias V

Current to equilibrated electrons
from p zone to n zone.
I diffusion  C exp[( E f  Eg  e  eV ) / k BT ]
I  I diffusion  I drift  I o exp( eV / k BT )  1
Diode Avalanche Breakdown
Diode –
equivalent
circuit