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Semiconductor Manufacturing
Silicon Chips
By Drew Brumm
Creating the Silicon Wafers
• Wafer growing process
– Similar to elementary science class (string in sugar water)
• A seed crystal of silicon is immersed in a bath of molten silicon,
and slowly pulled out.
– Crystal growth occurs uniformly in all directions
• This pulling process lasts for around 24 hours
– Creating ingot with diameter larger than desired.
– Ingot is ground down to required diameter and the end is cut off
• The ingot is then sliced into very thin wafers
– These wafers must be finely polished to meet surface flatness and
thickness specifications.
The Mask-Making Process
• Composite of Mask
– Film of chromium on a pure quartz glass plate.
– Finished plates are called Reticles
• Design of Mask
– Reticles are manufactured by very sophisticated and expensive
pattern generation equipment driven by the chip design database.
– As more components are placed on
each chip
• More complex patterns are drawn
• Which adds to the time to write the mask
– Driven by new product acceleration.
• Each new design or die shrink requires new
mask tooling
Epitaxy
• Epitaxial Growth
– Process of depositing a thin layer
• 0.5 to 20 microns of single crystal material onto wafer
– Must be ultra pure
• In order to create best possible quality of silicon
• Contaminant free for the construction of transistors
– Called the epi-layer
• Usually 3% or less of original wafer thickness.
Photolithography
• How photolithography works
– Process of transferring a pattern from mask to surface
of a silicon wafer.
• Current Method
– Wafer is coated with photoresist material
– Reticle(Mask) is exposed by laser through lens system
onto the wafer one die or a few at a time. Until entire
wafer has been exposed
– Similar to creating a photograph by
means of a very sophisticated
photographic negative.
Oxidation & Exposure
• Once Lithography has spun on photoresist
– Baked to create harder surface
– Then expose to reticle step by step creating
pattern on wafer.
– Implant process would destroy photoresist
so next process is to move photoresist to
tougher oxide layer.
Etch & Strip
• Etch Process can be wet or dry
– Wet eats away but is not easily manageable.
• Once on, beyond control could eat away at sides.
– Dry controllable costly
• Uses gas excited by radio freq generates plasma state.
– Remove oxide layer
• Were photoresist patter is not present.
• Stripping Process
– Photoresist has served its purpose and must be removed
• Photoresist must be entirely removed since it consists of organic
materials which if left on wafer surface will cause defects
• Use both wet and dry techniques to strip this layer away from wafer.
Diffusion & Implant
• Classic approach to creating electrical pockets
– Deposit material such as Boron on surface
• Drive into surface of silicon by exposing to controlled
periods of high temperature. Causes side ways diffusion
• Device geometries are becoming smaller diffusion
harder to deal with
• Improved approach
– Ion implantation process
• Material is implanted vertically into surface
by high energy ion beams penetrating silicon
vertically without any side ways diffusion
Deposition
• Removal and regrowth of oxide layer
– Repeat lithography, etch and strip processes with different mask to
create a window opening in the oxide were the transistor gate is
built.
– The gate is a conductive layer which is separated from the silicon
by a thin gate oxide.
– Positive electrical charge on the gate will create an opposite
negative field in the surface of the silicon
– This creates a conductive channel between the source and the
drain, letting current flow between them.
– Gate must be thin to allow electrical field to transfer across
insulator usually made by depositing silicon nitride film
Oxidation
• Oxides are grown or deposited
– Used to insulate or protect formed transistors
– Also used to insulate from its adjacent transistors
– Dielectric isolation oxides
• Used to insulate transistors from interconnection layers which
will be built above
– Passive oxides
• Deposited on top of competed wafers to protect the surface
from damage.
Interconnect Vias
• Photolithography again
– Used to create holes etched down to the three
transistor regions which will be connected to
other components on the chip
– Holes (Vias) are essentially chemically drilled
holes which expose the contacts to the three
terminals of the transistor.
Interconnect – Metallization
• A layer of aluminum is deposited on the surface and down into the via
holes
– Excess aluminum is etched away after another photolithography process
• Another layer of dielectric oxide
– Insulate the first layer of aluminum
from the next one
• Problems
– Contours create obstacles or steps which make
it difficult to lay down next metal layer. It is highly
desirable to smooth the surface between steps.
– Chemical Mechanical Planariazaion
• Used to smooth surface circular sanding action polishes the
surface of the wafer smooth
Interconnect – Cont
• After Chemical Mechanical Planarization
– Another set of Via holes etched in the oxide
– Contact plugs are deposited
• Usually made from tungsten or titanium
• Allows connection between two layers of aluminum
– After plug is in next layer of aluminum is deposited
• This process can be repeated up to 6 layers for very
complex logic chips Memory chips usually on have 2
Inspection & Measurement
• Inspection and Measurement is Critical
– Chip making deals with so many state-of-the-art
materials, and methods with small features and
precision, that the ability to measure and monitor the
process is vital.
– Inspection deals with tools that deal with sub-micron
levels, scanning electron microscopes must be used.
– As Geometries get size down to .2 micros the ability to
observe these defects becomes more challenging and
expensive.
Infrastructure - Yield
• Defects kill yield and drive up cost
– Inspection is vital in Fabrication.
• What a defect causes
– Cause electrical short circuits
– Open circuits or breaks in aluminum traces
• Causes of Defects
– Atmosphere in the Fabrication process
• Must have ultra clean room requirement
– Materials Used or tools that were used
– The smaller the die the larger the population of die per wafer and
the lower the statistical impact of the defects
Assembly & Packaging
• Assimilation of Die
– Wafer arrives with reject die marked with ink
– Saw between each die in both directions separating the
good die out
– Die’s are die bonded or attached onto the frame of a
package either epoxy or with silicon metal eutectic bond
– Then each die pin is connected using thin gold or
aluminum wire
– Bonded die and frame are sealed either by a molded
plastic compound or by attachment of a sealed lid
– Depending on the package type, the pins or leads may
have to be trimmed and formed to desired shape or use in
applications.
Recources
• http://www.processpecialties.com/siliconp.htm
• http://www.infras.com
• http://www.facsnet.org/tools/sci_tech/tech/fun
daments/semimfg.php3
• http://www.mcc.ac.uk/cem/hydrogen/hydroge
n.html
• http://www.microchrometechnology.com/info_7.p
hp