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Design and Implementation of VLSI Systems
(EN0160)
Prof. Sherief Reda
Division of Engineering, Brown University
Spring 2007
[sources: Weste/Addison Wesley – Rabaey/Pearson]
pn-junction reminder
A
Al
p
n
B
One-dimensional
representation
depletion region fixed ions
(almost no mobile carriers)
• Depletion region has associated capacitance
• When the diode is reversed biased (supposedly cutoff), tiny current
based on the minority carries still flows
• Transistor has two p-n diodes
Gate Capacitance
• Approximate channel as connected to source
• Cgs = eoxWL/tox = CoxWL = CpermicronW
• Cpermicron is typically about 2 fF/mm
polysilicon
gate
W
tox
n+
L
p-type body
n+
SiO2 gate oxide
(good insulator, eox = 3.9e0)
Source/Drain diffusion capacitance
• Csb, Cdb
Channel-stop implant
NA1
• Undesirable, called parasitic
capacitance
Side wall
• Capacitance depends on area and Source
W
ND
perimeter
– Use small diffusion nodes
– Comparable to Cg
xj
– Varies with process
Bottom
Side wall
LS
Channel
SubstrateNA
Transistor resistance
In the linear region
• Not accurate, but at least shows that the resistance is proportional
to L/W and decreases with Vgs
• If R/C are for a unit size transistor then a transistor of K unit
width has KC capacitance and R/K resistance
• The resistance of a PMOS transistor = 2× resistance of NMOS
transistor of the same size
Switch-level RC models
• Use equivalent circuits for MOS transistors
– Ideal switch + capacitance and ON resistance
– Unit nMOS has resistance R, capacitance C
– Unit pMOS has resistance 2R, capacitance C
• Capacitance proportional to width
• Resistance inversely proportional to width
d
g
d
k
s
s
kC
R/k
kC
2R/k
g
g
kC
kC
s
d
k
s
kC
g
kC
d
Inverter RC delay estimate
• Estimate the delay of a fanout-of-1 inverter
2C
R
A
2 Y
2
1
1
2C
2C
2C
Y
R
C
C
d = 6RC
2C
R
C
C
C
Fallacies
1. Increasing Vds does not increase the
saturation current
2. The transistor does not conduct in cutoff
3. The saturation current increases
quadratically for linear increases in Vgs
4. Transistor temperature can be ignored
Channel length modulation
GND
Source
• The reverse-bias p-n junction between drain
and body forms a depletion region with a width
Ld that increases with Vdb
• Increasing Vds
 increases depletion width
 decreases channel length
 increases current
Channel length
modulation factor
(empirical factor)
VDD
Gate
VDD
Drain
Depletion Region
Width: Ld
n+
L
Leff
n+
p GND
bulk Si
Leakage current
Tunnel current
polysilicon
gate
W
t ox
L
n+
n+
p-type body
Subthreshold conduction
Junction leakage
 Subthreshold leakage is
the biggest source in
modern transistors
Vgs Vt
I ds  I ds 0e
nvT
I ds 0   vT2 e1.8
Vds

v
 1  e T

n = 1.4-15



180nm process
At high electric field, drift velocity rolls
of due to carrier scattering
u n (m /s )
Velocity saturation
usat= 105
Constant velocity
Constant mobility (slope = µ)
xc = 1.5
Empirically:
With channel length modulation
x
(V/µm)
Temperature dependence
Summary
• Today:
– Transistor RC delay models
– Nonideal transistor operation
• Next time:
– SPICE tutorial