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Threshold Voltage Assignment to
Supply Voltage Islands in Corebased System-on-a-Chip Designs
Project Proposal:
Gall Gotfried
Steven Beigelmacher
02/09/05
Overview
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Introduction
Related Work
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Design Space
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What has already been done
What we plan to do
Milestones
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Deadlines we intend to keep
Introduction
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Trends in Design
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As process technology improves, more devices will
be integrated onto a chip, designs will grow more
complex
The scope of future designs will increasingly make
SoC attractive
Importance of Low Power
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Despite what designers previously thought, the
power problem has not been solved
Need proven techniques that will continue to be
effective with future technology nodes
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Vdd and Vth assignment
Introduction
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Need low power techniques that work in an
SoC framework
An SoC design:
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Hard and soft IP blocks that have been independently
characterized
The number of blocks may range from a handful up to one
hundred
There may already be an initial placement of blocks within a
defined die size
We probably don’t have the freedom to tweak
parameters within a core
Low power techniques must exist at the intracore level
Introduction
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Voltage islands are regions where nearby IP
blocks may use a supply voltage different
from the full-chip supply
We propose taking voltage islands in a corebased SoC design, and adding Vth
assignments and latency measures
It looks a lot like a placement problem
(simulated annealing, quadratic placement,
etc)
Related Work
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Reduction of power in a system-on-chip
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Set number of cores
Set die size
Tool used to move around cores based on
common supply voltage
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These common core sections are referred to as voltage
islands
Cores have several operating supply voltages
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Algorithm finds optimal placement of cores
Related Work
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Algorithm considers in placement
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Wire lengths
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Minimizes the length of wires between cores
Minimum number of islands
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Reduces the number of voltage converters
More Related Work
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Fine grained supply and threshold voltage
selection
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Gate level partitioning instead of core based
Balance between Vdd and Vth is kept to maintain
maximum performance
Frequency island partitioning
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Cores are partitioned based on minimum operating
frequency
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Reduces clock skew
Communication queues are required for inter-core
operations
Design Space
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Code exists to take an initial placement and create a
placement maximizing the use of voltage islands (Vdd
only)
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First step is implement algorithm from previous
voltage island paper and attempt to match results
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But we can’t get access to it
Still unsure about implementation approach: Simulated
annealing, integer linear programming, topological heuristic,
etc
Also need to generate comparable benchmarks
Then our work really begins
Design Space
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Need to extend baseline implementation to
handle Vth assignment
Examining multi-pass solutions (first assign
Vdds, then Vth, and so on – or start with Vth)
Concern about convergence using a single
solution pass via simulated annealing
Need to take the latencies of IP blocks into
account
If time permits, we hope to evaluate a few
alternative solutions for comparison
Milestones
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Previous work exploration
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Extend Algorithm
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Begin implementing algorithm for Vdd island partitioning
Deadline 02/23/2005
Test benchmarks on Vdd algorithm to attain similar results
as paper suggests
Begin extending algorithm to include optimum Vth
assignment
Deadline 03/21/2005
Achieve Results
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Test algorithm performance on benchmarks used in Vdd only
algorithm
Deadline 04/11/2005
You Got Questions
We Got Answers