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MM54HC354/MM74HC354/
MM54HC356/MM74HC356
8-Channel TRI-STATEÉ Multiplexers with Latches
General Description
The MM54HC354/MM74HC354 and MM54HC356/
MM74HC356 utilize advanced silicon-gate CMOS technology. They exhibit the high noise immunity and low power dissipation of standard CMOS integrated circuits, along with
the ability to drive 15 LS-TTL loads. Due to the large output
drive capability and the TRI-STATE feature, these devices
are ideally suited for interfacing with bus lines in a bus organized system.
These data selectors/multiplexers contain full on-chip binary decoding to select one of eight data sources. The data
select address is stored in transparent latches that are enabled by a low level address on pin 11, SC. Data on the 8
input lines is stored in a parallel input/output register which
in the MM54HC354/MM74HC354 is composed of 8 transparent latches enabled by a low level on pin 9, DC, and in
the MM54HC356/MM74HC356 is composed of 8 edge-triggered flip-flops, clocked by a low to high transition on pin 9,
CLK. Both true (Y) and complementary (W) TRI-STATE outputs are available on both devices.
The 54HC/74HC logic family is functionally as well as pinout compatible with the standard 54LS/74LS-TTL logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.
Features
Y
Y
Y
Y
Y
Y
Y
Transparent latches on data select inputs
Choice of data registers:
Transparent (’354)
Edge-triggered (’356)
TRI-STATE complementary outputs with fanout
of 15 LS-TTL loads
Typical propagation delay:
Data to output (’354): 32 ns
Clock to output (’346): 35 ns
Wide power supply range: 2V – 6V
Low quiescent supply current: 80 mA maximum
Low input current: 1 mA maximum
Connection Diagram
Dual-In-Line Package
TL/F/5208 – 1
Top View
Order Number MM54HC354/356 or MM74HC354/356
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/F/5208
RRD-B30M105/Printed in U. S. A.
MM54HC354/MM74HC354/MM54HC356/MM74HC356
8-Channel TRI-STATE Multiplexers with Latches
June 1992
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VCC)
DC Input or Output Voltage
(VIN, VOUT)
b 0.5V to a 7.0V
Supply Voltage (VCC)
b 1.5V to VCC a 1.5V
DC Input Voltage (VIN)
b 0.5V to VCC a 0.5V
DC Output Voltage (VOUT)
g 20 mA
Clamp Diode Current (ICD)
g 35 mA
DC Output Current, per pin (IOUT)
g 70 mA
DC VCC or GND Current, per pin (ICC)
b 65§ C to a 150§ C
Storage Temperature Range (TSTG)
Power Dissipation (PD)
(Note 3)
600 mW
S.O. Package only
500 mW
Lead Temp. (TL)
(Soldering 10 seconds)
Operating Temp. Range (TA)
MM74HC
MM54HC
Min
2
Max
6
0
VCC
Units
V
V
b 40
b 55
a 85
a 125
§C
§C
1000
500
400
ns
ns
ns
Input Rise or Fall Times
VCC e 2.0V
(tr, tf)
VCC e 4.5V
VCC e 6.0V
260§ C
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
VCC
TA e 25§ C
Typ
74HC
54HC
TA eb40 to 85§ C TA eb55 to 125§ C Units
Guaranteed Limits
VIH
Minimum High Level Input
Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level Input
Voltage**
2.0V
4.5V
6.0V
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
V
VOH
Minimum High Level Output
Voltage
VIN e VIH or VIL
lIOUTl s20 mA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN e VIH or VIL
lIOUTl s6.0 mA
lIOUTl s7.8 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN e VCC or GND
VIN e VIH or VIL
lIOUTl s6.0 mA
lIOUTl s7.8 mA
VOL
Maximum Low Level Output
Voltage
VIN e VIH or VIL
lIOUTl k20 mA
IIN
Maximum Input Current
6.0V
g 0.1
g 1.0
g 1.0
mA
IOZ
Maximum TRI-STATE Output VOUT e VCC or GND
Leakage Current
G1 e VIH
6.0V
g 0.5
g 5.0
g 10
mA
8.0
80
160
mA
ICC
Maximum Quiescent Supply
Current
VIN e VCC or GND
IOUT e 0 mA
6.0V
Note 1: Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C.
Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and
IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
**VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89.
2
AC Electrical Characteristics VCC e 5V, TA e 25§ C, tr e tf e 6 ns
MM54HC354/MM74HC354
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
tPHL, tPLH
Maximum Propagation
Delay D0–D7 to either Output
CL e 45 pF
32
46
ns
tPHL, tPLH
Maximum Propagation
Delay DC to either Output
CL e 45 pF
38
53
ns
tPHL, tPLH
Maximum Propagation
Delay S0–S2 to either Output
CL e 45 pF
40
56
ns
tPHL, tPLH
Maximum Propagation
Delay SC to either Output
CL e 45 pF
42
58
ns
tPZH, tPZL
Maximum Output Enable Time
RL e 1 kX
CL e 45 pF
17
24
ns
tPHZ, tPLZ
Maximum Output Disable Time
RL e 1 kX
CL e 5 pF
23
32
ns
tS
Minimum Setup Time
D0–D7 to DC, S0–S2 to SC
3
10
ns
tH
Minimum Hold Time
D0–D7 to DC, S0–S2 to SC
0
5
ns
tW
Minimum Pulse Width, SC or DC
10
15
ns
Conditions
Typ
Guaranteed
Limit
Units
MM54HC356/MM74HC356
Symbol
Parameter
tPHL, tPLH
Maximum Propagation
Delay CLK to either Output
CL e 45 pF
35
50
ns
tPHL, tPLH
Maximum Propagation
Delay S0–S2 to either Output
CL e 45 pF
40
56
ns
tPHL, tPLH
Maximum Propagation
Delay SC to either Output
CL e 45 pF
42
58
ns
tPZH, tPZL
Maximum Output Enable Time
RL e 1 kX
CL e 45 pF
17
24
ns
tPHZ, tPLZ
Maximum Output Disable Time
RL e 1 kX
CL e 5 pF
23
32
ns
tS
Minimum Setup Time
D0–D7 to CLK, S0–S2 to SC
3
10
ns
tH
Minimum Hold Time
D0–D7 to CLK, S0–S2 to SC
0
5
ns
tW
Minimum Pulse Width, SC or CLK
10
15
ns
3
AC Electrical Characteristics MM54HC354/MM74HC354 (Continued)
VCC e 2.0 – 6.0V, CL e 50 pF, tr e tf e 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
VCC
TA e 25§ C
Typ
tPHL, tPLH
tPHL, tPLH
tPHL, tPLH
tPHL, tPLH
tPZH, tPZL
Maximum Propagation
Delay D0–D7 to either Output
Maximum Propagation
Delay DC to either Output
Maximum Propagation
Delay S0–S2 to either Output
Maximum Propagation
Delay SC to either Output
Maximum Output Enable Time
74HC
TA eb40 to 85§ C
54HC
TA eb55 to 125§ C
Units
Guaranteed Limits
CL e 50 pF
CL e 150 pF
2.0V
2.0V
90
100
235
275
294
344
352
412
ns
ns
CL e 50 pF
CL e 150 pF
4.5V
4.5V
35
40
47
55
59
68
70
83
ns
ns
CL e 50 pF
CL e 150 pF
6.0V
6.0V
26
32
40
46
50
58
60
69
ns
ns
CL e 50 pF
CL e 150 pF
2.0V
2.0V
115
125
270
310
337
387
405
465
ns
ns
CL e 50 pF
CL e 150 pF
4.5V
4.5V
40
46
54
62
68
78
82
93
ns
ns
CL e 50 pF
CL e 150 pF
6.0V
6.0V
32
38
46
52
58
66
69
78
ns
ns
CL e 50 pF
CL e 150 pF
2.0V
2.0V
120
130
285
325
356
406
427
488
ns
ns
CL e 50 pF
CL e 150 pF
4.5V
4.5V
42
50
57
65
71
81
86
97
ns
ns
CL e 50 pF
CL e 150 pF
6.0V
6.0V
34
40
48
55
60
69
72
82
ns
ns
CL e 50 pF
CL e 150 pF
2.0V
2.0V
120
110
300
340
375
425
450
510
ns
ns
CL e 50 pF
CL e 150 pF
4.5V
4.5V
45
52
60
68
75
85
90
102
ns
ns
CL e 50 pF
CL e 150 pF
6.0V
6.0V
36
42
51
58
64
72
77
87
ns
ns
RL e 1 kX
CL e 50 pF
CL e 150 pF
2.0V
2.0V
50
60
125
165
156
206
188
248
ns
ns
CL e 50 pF
CL e 150 pF
4.5V
4.5V
18
25
25
33
31
41
38
49
ns
ns
CL e 50 pF
CL e 150 pF
6.0V
6.0V
15
21
21
28
26
35
32
42
ns
ns
RL e 1 kX
CL e 50 pF
2.0V
4.5V
6.0V
68
24
20
165
33
28
206
41
35
248
49
42
ns
ns
ns
tPHZ, tPLZ
Maximum Output Disable Time
tS
Minimum Setup Time
D0 – D7 to DC, S0–S2 to SC
2.0V
4.5V
6.0V
6
3
3
50
10
10
60
13
13
75
15
15
ns
ns
ns
tH
Minimum Hold Time
D0 – D7 to DC, S0–S2 to SC
2.0V
4.5V
6.0V
0
0
0
5
5
5
5
5
5
5
5
5
ns
ns
ns
tW
Minimum Pulse Width
SC or DC
2.0V
4.5V
6.0V
30
10
10
80
16
15
100
20
18
120
24
20
ns
ns
ns
tTLH, tTHL
Maximum Output Rise
and Fall Time
CL e 50 pF
2.0V
4.5V
6.0V
25
7
6
60
12
10
75
15
13
90
18
15
ns
ns
ns
CPD
Power Dissipation Capacitance
(Note 5)
(per package)
Active
TRI-STATE
150
50
pF
pF
CIN
Maximum Input Capacitance
5
10
10
10
pF
COUT
Maximum Output Capacitance
15
20
20
20
pF
Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC.
4
AC Electrical Characteristics MM54HC356/MM74HC356 (Continued)
VCC e 2.0–6.0V, CL e 50 pF, tr e tf e 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
VCC
TA e 25§ C
Typ
tPHL, tPLH
tPHL, tPLH
tPHL, tPLH
tPZH, tPZL
Maximum Propagation
Delay CLK to either Output
Maximum Propagation
Delay S0–S2 to either Output
Maximum Propagation
Delay SC to either Output
Maximum Output Enable Time
74HC
TA eb40 to 85§ C
54HC
TA eb55 to 125§ C
Units
Guaranteed Limits
CL e 50 pF
CL e 150 pF
2.0V
2.0V
100
110
225
295
318
369
338
442
ns
ns
CL e 50 pF
CL e 150 pF
4.5V
4.5V
36
42
51
59
63
73
76
90
ns
ns
CL e 50 pF
CL e 150 pF
6.0V
6.0V
28
34
43
50
53
63
64
75
ns
ns
CL e 50 pF
CL e 150 pF
2.0V
2.0V
120
130
285
325
356
406
427
488
ns
ns
CL e 50 pF
CL e 150 pF
4.5V
4.5V
42
50
57
65
71
81
86
97
ns
ns
CL e 50 pF
CL e 150 pF
6.0V
6.0V
34
40
48
55
60
69
72
82
ns
ns
CL e 50 pF
CL e 150 pF
2.0V
2.0V
120
110
300
340
375
425
450
510
ns
ns
CL e 50 pF
CL e 150 pF
4.5V
4.5V
45
52
60
68
75
85
90
102
ns
ns
CL e 50 pF
CL e 150 pF
6.0V
6.0V
36
42
51
58
64
72
77
87
ns
ns
RL e 1 kX
CL e 50 pF
CL e 150 pF
2.0V
2.0V
50
60
125
165
156
206
188
248
ns
ns
CL e 50 pF
CL e 150 pF
4.5V
4.5V
18
25
25
33
31
41
38
49
ns
ns
CL e 50 pF
CL e 150 pF
6.0V
6.0V
15
21
21
28
26
35
32
42
ns
ns
RL e 1 kX
CL e 50 pF
2.0V
4.5V
6.0V
68
24
20
165
33
28
206
41
35
248
49
42
ns
ns
ns
tPHZ, tPLZ
Maximum Output Disable Time
tS
Minimum Setup Time
D0–D7 to CLK, S0–S2 to SC
2.0V
4.5V
6.0V
6
3
3
50
10
10
60
13
13
75
15
15
ns
ns
ns
tH
Minimum Hold Time
D0–D7 to CLK, S0–S2 to SC
2.0V
4.5V
6.0V
0
0
0
5
5
5
5
5
5
5
5
5
ns
ns
ns
tW
Minimum Pulse Width
SC to CLK
2.0V
4.5V
6.0V
30
10
10
80
16
15
100
20
18
120
24
20
ns
ns
ns
tr, tf
Maximum Clock Input
Rise and Fall Time
2.0V
4.5V
6.0V
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
tTLH, tTHL
Maximum Output Rise
and Fall Time
CL e 50 pF
60
12
10
75
15
13
90
18
15
ns
ns
ns
CPD
Power Dissipation Capacitance
(Note 5)
(per package)
Active
TRI-STATE
2.0V
4.5V
6.0V
25
7
6
150
50
pF
pF
CIN
Maximum Input Capacitance
5
10
10
10
pF
COUT
Maximum Output Capacitance
15
20
20
20
pF
Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC.
5
Function Table
Inputs
Select ²
Data
Control
’HC354
Clock
’HC356
Output
Enables
Outputs
S1
S2
S0
DC
CLK
G1
G2
G3
W
Y
X
X
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
X
X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X
X
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
X
X
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Z
Z
Z
D0
D0n
D1
D1n
D2
D2n
D3
D3n
D4
D4n
D5
D5n
D6
D6n
D7
D7n
Z
Z
Z
D0
D0n
D1
D1n
D2
D2n
D3
D3n
D4
D4n
D5
D5n
D6
D6n
D7
D7n
u
H or L
u
H or L
u
H or L
u
H or L
u
H or L
u
H or L
u
H or L
u
H or L
H e high level (steady state)
L e low level (steady state)
X e irrelevant (any input, including transitions)
Z e high-impedance state (off state)
u e transition from low to high level
D0 . . . D7 e the level steady-state inputs at inputs D0 through D7, respectively, at the time of the low-tohigh clock transition in the case of ’HC356
D0n . . . D7n e the level of steady state inputs at inputs D0 through D7, respectively, before the most
recent low-to-high transition of data control or clock.
² This column shows the input address set-up with SC low.
6
Logic Diagram
Ê HC354
TL/F/5208 – 2
7
Logic Diagram
Ê HC356
TL/F/5208 – 3
8
9
MM54HC354/MM74HC354/MM54HC356/MM74HC356
8-Channel TRI-STATE Multiplexers with Latches
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MM54HC354J, MM54HC356J, MM74HC354J or MM74HC356J
NS Package Number J20A
Molded Dual-In-Line Package (N)
Order Number MM74HC354N or MM74HC356N
NS Package Number N20A
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