Download Problem 1 Logic Design | Logical Effort Assume the

Problem 1 Logic Design | Logical Effort
Assume the mobility ratio, μ n / μ p = 1.5, CS/D = CG = C0.
VDD
A
24
C
12
D
8
12
B
Out
6
B
A
12
C
12 D
12
a. What is the logic function of Out?
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Out = A + B（C + D）
b. Which input has the least average delay to the output?
A
B
C
D
Justification: Closest to output
c. What are the largest g avg (average worst-case g up and g down for an input) and largest
p avg (average worst-case p up and p down for an input)?
Largest g avg is either a or c (large input cap)
36
36
, 𝑔𝐴,𝑢𝑝 =
,𝑔
= 3.3
𝑔𝐴,𝑑𝑛 =
30
6.7 𝐴,𝑎𝑣𝑔
24
24
𝑔𝐶,𝑑𝑛 =
, 𝑔𝐶,𝑢𝑝 =
,𝑔
=3
10
6.7 𝐶,𝑎𝑣𝑔
Largest pavg is either c or d (small reference invertor)
38
38
𝑝𝐶,𝑑𝑛 =
,𝑝
=
,𝑝
= 4.75
10 𝐶,𝑢𝑝 6.7 𝐶,𝑎𝑣𝑔
38
38
, 𝑝𝐷,𝑢𝑝 =
,𝑝
= 4.75
𝑝𝐷,𝑑𝑛 =
10
6.7 𝐷,𝑎𝑣𝑔
Max (gavg) = 3.3 (A)
Max (pavg) = 4.75 (C D)
Problem 2 Flip-Flops | Logical Effort
Clk
S
Q
D
Clk 1
Fig. 2: Sequential circuit.
All transistors in the circuit have equivalent resistance R and gate capacitance C (ignore
diffusion capacitances). Output ̅ is loaded with external capacitance CL = 16C.
Calculate the propagation delay tClk-Q (to output ̅Q) for high-to-low and low-to-high
transitions. Ignore signal slopes in the delay calculation.
tpHL = 0.69 (3R⋅2C + R⋅4C + R⋅16C) = 0.69⋅26RC = 17.94 RC (stack PD + 2nd stage PU + inv PD)
tpLH = 0.69 (3R⋅4C + R⋅16C) = 0.69⋅28RC = 19.32 RC (2nd stage PD + inv PU)
tpLH = 17.94 RC
tpHL = 19.32 RC