Download Project Three – BJT Amplifier

Project Three – BJT Amplifier
EENG 3510 – Electronics 1
Spring 2012
Joshua Jenkins
Joshua Jenkins
May 2, 2012
Abstract
Project three was to design and build the first stage of a three-stage amplifier using an NPN
bipolar junction transistor (BJT) to amplify a small signal. The BJT will be used in a commonemitter configuration and will be biased using a constant current source called a current mirror.
Introduction
The objective for project three is to design and build the first stage of a three-stage small signal
amplifier in PSpice using an NPN bipolar junction transistor (BJT). Unlike the NMOS used in
project two, the BJT only has three pins: The collector (C), the base (B), and the emitter (E). The
BJT is used in the common-emitter configuration, similar to the common-source configuration
used in project two.
The construction of the NPN BJT is similar to the NMOS, only that the base is connected directly
to the p-type substrate in the transistor, and therefor will allow current to flow. This makes the
analysis slightly more complicated than the NMOS, and changes how the operating modes are
determined. Unlike the NMOS, the BJT is biased using a constant current source, called a
current mirror, connected to the emitter. This biasing will ensure that the BJT works in “active
mode” so that it can be used as an amplifier.
Problem and Constrains
Impressed by your previous work, your boss asks you to contribute to another project. This
time, your responsibility is to design the first stage of what will be a three-stage amplifier, using
a BJT process.
To improve upon our design from out first amplifier using the NMOS, the conditions for the
new BJT amplifier have changed slightly. The target gain has increased and the signal swing has
significantly decreased. However, we are allowed a slightly higher consumption of power. The
additional condition for biasing the BJT using a current mirror has also been added.




Must use a current mirror for biasing.
Voltage gain of at least 50V/V.
Power consumption of no more than 0.5mW.
Allowable signal swing at the output of at least 0.3V in both directions.
Design
Operation Modes
A BJT is able to function in four possible modes. Each is shown in Table 1.1.
Joshua Jenkins
May 2, 2012
Figure 1.1
Table 1.1
Mode
EBJ
CBJ
Cutoff
Active
Reverse
Forward
Reverse
Reverse
Reverse Active
Saturation
Reverse
Forward
Forward
Forward
In Figure 1.1, we can see that there are two junctions in the BJT. On a diode, the p-type
substrate is connected to the anode (+) and the n-type is connected to the cathode (-). When
there is a positive voltage across the diode (the voltage on the anode is greater than the voltage
on the cathode) the diode will operate in the forward region. When there is a negative voltage
across the diode, it will operate in the reverse region. The two junctions in the BJT operate the
same way as a diode. For example, when the voltage on the base (B) is greater than that of the
collector (C), the junction joining the two, called the collector-base junction (CBJ), will operate
in the forward region.
To function as an amplifier, the BJT must be biased to work in active mode. Table 1.1 shows
that for active mode, the EBJ and CBJ junctions operate in the forward and reverse regions
respectively. In general, there are two conditions to be satisfied. First, the voltage on the base
(VB) must be less than the voltage on the collector (VC) plus the threshold voltage. Second, the
voltage on the base must be higher than the voltage on the emitter (VE) plus the threshold
voltage. The threshold voltage will be said to be 0.5V.


VB < VC + 0.5V
VB > VE + 0.5V
These conditions are derived for an ideal BJT. However, for our amplifier we will use a more
realistic model for our BJT. For a non-ideal BJT, our two conditions are slightly changed.


VBE = VB - VE ≈ 0.7V
VCE = VC - VE > 0.3V
These two new conditions are more specific, and fortunately make our analysis easier.
Joshua Jenkins
May 2, 2012
Figure 1.2
Diagrams
Figure 1.2 shows the hand drawn diagram for
the ideal circuit used for our NPN BJT
amplifier. On the emitter is the ideal current
source labeled I. However, to implement our
design, that ideal current source must be
replaced with a current mirror (Figure 1.3).
The current mirror uses two more BJTs to
provide a constant current for the emitter.
Figure 1.3
Combining these two circuits we can draw
the final circuit diagram (Figure 1.4) that will
be used for our amplifier. Each node is
labeled so that the circuit can be entered
into a PSpice text file and then simulated. VO
is connected directly to the collector at node
4. VBE is the voltage across node 3 and node
6 and VCE is the voltage across node 4 and
node 6.
Figure 1.4
Joshua Jenkins
May 2, 2012
For our amplifier, we can also assume the following condition.

IC ≈ IE
That is the current on the collector is roughly equal to the current on the emitter. When the
BJT operates in active mode, the current on the emitter is equal to the sum of the current on
the base and the current on the collector (IE = IB + IC). From these two equations, we can also
assume that the current on the base (IB) is roughly equal to zero. From these conditions and
Equation 1.1, we observe that the β for our circuit must be very large.
Equation 1.1
Small Signal
Our input for the amplifier is a small signal AC voltage source (vsig) that is 1V. Our output
voltage vo divided by our small signal source determines the gain of our amplifier.
Gv = vo / vsig
In series with the input signal was input resistance (Rsig) of 10kΩ. The input is connected to the
base of the BJT circuit with a bypass capacitor (C1) set at a value of 10µF. In addition, the
emitter is connected to ground through another 10μF bypass capacitor (C2). Because of the
large capacitance of these two capacitors, they can be assumed as open when performing DC
analysis and shorted when performing small signal analysis.
Current Mirror
The current mirror is used to provide a constant current on the emitter of the BJT. This
constant current source will be used in our DC analysis to bias the BJT. The constant current (I)
will be equal to the emitter current (IE) which we have also assumed to be equal to the collector
current (IC).
I = IC = IE
This greatly simplifies how we will determine the value for the collector resistor (RC). The
current I is equal to IREF which is determined by using ohms law.
I = IREF = (VCC – VBE) / R1
Where VBE is simply 0.7V and VCC is our 3.3V power source. Therefor, the current I only
depends on the value of R1.
Joshua Jenkins
May 2, 2012
From the assumptions made thus far, we must simply determine the values of three resistors
that will determine how the amplifier works. These values must be chosen so that the output
of the amplifier meets all of our constraints.



RC
RB
R1
Performance Analysis
Before entering our circuit into Pspice, we must first design a circuit on paper to determine the
initial values of our unknown resistors. To do this, the analysis is split into two processes: DC
analysis and small signal analysis.
DC Analysis
For the DC analysis we can make a few changes to the overall circuit diagram. First, the bypass
capacitors are considered as open, and therefor anything connected to the pins of the BJT
through a capacitor can be ignored. Secondly, we can bring back the ideal current source in
place of the current mirror while determining a value for I. This leaves us with the diagram in
Figure 1.5.
Figure 1.5
We already know that VBE = 0.7V. Because IB is
essentially zero, VB is roughly VCC, and therefor VE =
2.6V. VC must always be greater than VE plus 0.3V.
However, to allow for a 0.3V swing, VC actually needs
to be greater than VE plus 0.6V and 0.3V less than VCC.
Therefor, VC needs to be greater than 3.2V. This
doesn’t leave much room, however we will see that
because VB isn’t exactly VCC we have more room to
work with.
We can first choose a low value for the current I such
as 1mA. In order to have a value of 1mA for I we
must plug this into our previous equation for the
current mirror. For I = 1mA, we calculate R1 = 5.2kΩ.
Joshua Jenkins
May 2, 2012
Small Signal Analysis
The small signal analysis will determine the overall gain of our amplifier. First, we redraw our
circuit diagram for small signal analysis (Figure 1.6). The means that we short any bypass
capacitors, short any DC voltage sources, and open and current sources. By doing this, anything
connected to VCC is now connected directly to ground. The emitter of the BJT is now connected
to ground as well.
Figure 1.6
The input voltage vi is determined by the voltage divider formed by Rsig and RB//rπ. The output
voltage vo is determined by multiplying the current gmvπ by Rc. The value gm is the transconductance of the BJT which is determined by the collector current IC. From these two
relationships, we can determine the overall gain of the amplifier.
|GV| = |(vo / vsig)| = |-gmRC*[(RB//rπ)/(RB//rπ + Rsig)]| > 50V/V
Because RB must be large, we will initially set RB = 1MΩ. rπ is determined by β / gm, which is
very large due to a large β (we can assume rπ to be 1MΩ). Therefor, based on our initial current
of 1mA for I, the value of RC must be greater than 1275Ω to have a gain greater than 50V/V.
We will set RC = 1.3kΩ for its initial value.
Testing
Now that we have our initial values, we can enter our design into Pspice for simulation. Testing
these values, we ended up achieving a gain of only about 7V/V. Because our BJT was not ideal
and our value of β was not infinity, we needed to compensate for the errors we made. After
some alterations to the values chosen and some trial and error, a gain of just over 50V/V was
reached, shown in Figure 1.7. The yellow line is used to show 50V/V. The maximum gain was
achieved at a frequency of roughly 3KHz.
Joshua Jenkins
May 2, 2012
Figure 1.7
Figure 1.8 shows the output file for our simulation. To test for swing, the voltage at node 4
should able to be increased by 0.3V in either direction and not go above V CC of 3.3V or drop
below VE + 0.3V. This is to ensure that the BJT works in active mode for the entire range of the
signal. We confirmed that our VC (boxed in yellow) of 0.7075V met that restriction.
Figure 1.8
Joshua Jenkins
May 2, 2012
PSpice netlist
Figure 1.9