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UNIVERSITY OF CALIFORNIA
College of Engineering
Department of Electrical Engineering and Computer Sciences
Last modified on August 16, 2007 by Elad Alon
Elad Alon
Lab #1: Circuit Simulation
EECS 141
Due Thursday, September 6th, 5pm, box in 240 Cory
1. Objective
The objective of this session is to give initial exposure to the software environment that will be
used in this course throughout the semester.
HSPICE (a circuit simulator) and Awaves (a waveform viewer) will be used to execute some of
the procedures that are necessary in many lab and homework assignments, in addition to your
project, during the course.
2. Tasks
a. Make sure your account is correctly setup and that you can log in to the instructional
servers (cory, quasar, pulsar).
You can find information about the organization of the ee141 master account (where you
will be copying files for the labs from) here:
http://bwrc.eecs.berkeley.edu/Classes/icdesign/ee141_f02/SoftwareLabs/class-setup.txt
Note that you do not need follow steps 1) - 3) described in the above document – they
were already taken when your account was automatically generated.
b. Copy the work files from the EE141 master account to your home directory. You may
want to do this as follows:
> mkdir LAB1
> cd LAB1
> cp ~ee141/LAB1/RTLinv.sp .
c. Examine the SPICE deck for the RTL inverter by typing in the following:
> cat RTLinv.sp
The file (RTLinv.sp) contains the description of a RTL (Resistor Transistor Logic)
inverter and the analyses to be performed by SPICE. The schematic of the circuit is
shown below in Figure 1.1
RTLinv.sp:
Simple RTL Inverter
.include ‘/home/ff/ee141/MODELS/npn.mod’
*netlist--------------------------------------VCC vcc 0 5
VIN in 0 PULSE 0 5 2NS 2NS 30NS 60NS
RB in base 10k
Q1 out base 0 NPN
RC vcc out 1k
*extra control information--------------------.options post=2 nomod
.op
*analysis-------------------------------------.TRAN 1ns 30ns
.DC VIN 0 5 0.1
.END
There are three main section in the spice deck:
 The netlist description. A netlist is a computer readable representation of the
circuit schematic.
 The models used. A model in SPICE contains the parameters of the equations
used by SPICE to analyze certain elements (such as transistors) in the circuit.
 The analysis to be performed during the simulation. We are requesting a
transient analysis and a DC analysis of the circuit.
d. Simulate the circuit netlist.
> hspice RTLinv.sp >! RTLinv.out
Upon proper completion of the simulation, you should see the following:
> info:
***** hspice job concluded
e. Definitions of the output files:






f.
RTLinv.sp is the input netlist (your file)
RTLinv.sw0 is the DC sweep data output (used by awaves)
RTLinv.tr0 is the transient data output (used by awaves)
RTLinv.out is the output listing from HSPICE (look here for errors or text about the
circuit)
RTLinv.st0 is the simulation run information (usually not useful)
RTLinv.ic0 is the information about the initial condition computed by HSPICE (usually
don’t need to look at this)
View the results of the transient analysis.
Load awaves and examine the results of the transient analysis by entering the following:
> awaves &
Once awaves loads, click on Design/Open. This will open a menu to select which netlist
file to display. Your netlist RTLinv.sp should be listed, otherwise, switch to the correct
directory using the tab or the arrows. Once you have found your netlist, double-click on
RTLinv.sp, which should open the Results Browser.
To view the transient waveforms, click on Transient: Simple RTL Inverter and either
double click on the waveform you wish to see or right click on the waveform and drag
the wave with the center mouse button to the panel you want to display the waveform.
Print the waveforms for in and out.
g. View the results of the DC analysis.
Open a new panel for the DC waveform by clicking on Panels/Add. Return to the
Results Browser or reopen by clicking Tools/Results Browser. Click on DC: Simple
RTL Inverter and repeat part f) to view the DC waveforms.
Print the waveform for out.
h. Transform the RTL gate into a NMOS inverter with a passive load.
Replace the bipolar transistor with a MOS transistor (refer to Figure 1.2)
M1
A model for the MOSFET must first be obtained. Replace npn.mod with scmos.mod in
the .include line of your netlist and save as MOSinv.sp.
Edit MOSinv.sp by replacing the BJT with a MOSFET in your netlist.
Delete:
Replace with:
i.
Q1 out base 0 npn
M1 out base 0 0 NMOS L=2u W=100u
Simulation and Analysis of the MOS inverter.
Repeat steps d-g, this time using MOSinv.sp as the input file.
3. Report
For your report, all that is required is the following:



A printout of the SPICE input files
Plot of the transient response of the pseudo-NMOS inverter
Plot of the DC transfer characteristic of the pseudo-NMOS inverter