Download 10 Logical/Physical Relationships 10.1 Logic states and Physical

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Prof. Dr. J. Reichardt
Prof. Dr. B. Schwarz
FB Elektrotechnik/Informatik
10
Logical/Physical Relationships
10.1 Logic states and Physical Levels
•
Useful notations and meaningful logic names have to be considered in order to bridge the gap between
the logic domain in which the digital device is designed and the physical domain in which the device is
to be operated.
Difference between :logical states: 0, 1
describe the logical
(Boolean) behaviour
physical levels: L(ow voltage), H(igh voltage)
describe the electrical behaviour
with voltage waveforms
Reason: The relationship 0 = L and 1 = H is only valid if we discuss so called positive logic.
External logic states or
physical level at the input
•
•
and
Internal logic
states
External logic states or
physical level at the output
Internal signals of switching device symbols will be described by logical states (0, 1).
External signals of switching device symbols may be described by logical states or by physical levels.
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Polarity Indicator
•
•
Some manufacturers– data books describe the circuit logic with function tables which use physical
levels L and H for inputs and outputs.
Physical level conversion of inputs and outputs is marked with a polarity indicator :
Quadruple 2 to 1 multiplexers
SN74AHC258
Triple 3- input positive nand gates
SN74AHC10
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Applying De Morgan–s law on gates with complemented inputs/outputs
¬A ∧ ¬B = ¬( A ∨ B)
¬A ∧ B = ¬( A ∨ ¬B)
therefore
therefore
•
By using DeMorgan–s law, the logic expression for gates with complemented interface signals can be
manipulated. As a result, two different symbols describe the same logic function.
•
Inversion bubbles (active low indicator bubble) and polarity indicators can be shifted from all inputs
to the output. The logic function has to change according to DeMorgan–s law.
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•
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Assignment of logic states to physical levels can be chosen
differently: positive logic or negative logic
logic
symbol
function
table
positive logic
a
L
L
H
H
b
L
H
L
H
a
0
0
1
1
b
0
1
0
1
H → 1, L → 0
a b Y
1 1
0
1 0
0
0 1
0
0 0
1
logic
symbol
Y
1
1
1
0
→ NAND
Y
H
H
H
L
negative logic
external physical levels
truth
tables
negative logic
positive logic
L(ow voltage)
H(igh voltage)
L → 1, H → 0
a b Y
0 0
1
0 1
1
1 0
1
1 1
0
→ NOR
•
a
1
1
1
0
b
1
0
1
0
Compared with truth tables function tables
offer a more precise description because L(ow)
and H(igh) denote the input and output signal
levels so there is no ambiguity about the
electrical function.
Y
0
0
0
1
•
Truth tables which use either positive or
negative logic can be derived from a function
table.
external logic states
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10.2 Open-Drain/Open-Collector Device Output Stages
Totem-pole output driver stage (standard push-pull)
(bipolar)
(MOS)
Open-collector / open-drain output
(bipolar)
(MOS)
•
Open-collector /open-drain gates omit the entire upper half of the output stage. Only a passive pull-up
to High state is provided by an external resistor.
•
During an output transition from L → H the charging of a load capacitor will take 5 to 10 times
longer than when discharging from a H → L transition because the pull-up resistor is responsible for
a larger charging time constant. The on-resistance of the switching transistor to ground is much less
than that of the pull-up.
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Interfacing of open-collector / open-drain output stages
•
Logic symbol: NAND-gate with open-collector / drain output stage:
Open-Collector/
Drain Symbol
•
•
Function table: Link up of two open-drain outputs:
the interconnection of several open-collector / -drain
outputs with an external pull-up resistor will provide
an
............ function: wired-............
Function Table
B A
Y
L L
L H
H L
H H
A
74HC03
B
74HC03
•
A
Complete logic function with two inputs per NANDgate:
Y = ¬(I1 ∧I2) ...... ¬(I3 ∧ I4)
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Open-collector / drain Bus
•
Each bus driver is controlled by an output enable input.
•
Only one enable should be High at a time.
DATA1
DATA2
DATA_n
•
The output ¬DATA_i represents the inverted data bit of the enabled bus driver stage.
•
A wired-AND logic with interconnected open-collector NAND-outputs represents a NOR logic.
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10.3 Tri-State1 Output and Bidirectional Bus Driver Circuit
•
Tri-state driver function table and schematic:
(NMOS transistors are switched ON with a H level
at the gate (D), PMOS transistors are switched ON
with a L level at the gate (C))
•
EN A B C D N
P
L
L
H
H
on H
L
H
L
H L L L off
Y
A tri-state driver operates in one of three
states “ logic 0, logic 1 or high-impedance (Z)
state. In the Z or disconnect state the tri-state
driver is functionally ”floating䀕as if it where
not there.
Tri-state driver logic symbol:
1
High output current
Tri-state
output
Low active output
enable input
Tri-State is a trademark of National Semiconductor Corporation
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Bidirectional bus interface
•
By using tri-state and input drivers, a bus can
be built up which may be shared by multiple
data sources.
•
Only one data source is allowed to transmit
data onto the bus at any one time.
EN2 EN1 Direction of transmission
transmitter
receiver
0
1
0
1
0
0
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