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Transactions on Electrical Engineering, Vol. 2 (2013), No. 1
10
Control Techniques of Grid Connected PWM
Rectifiers under Unbalanced Input Voltage
Conditions
Martin Bejvl 1), Petr Šimek 2), Jiří Škramlík 3), Viktor Valouch 4)
Institute of Thermomechanics AS CR, v. v. i., Department of Electrical Engineering and Electrophysics,
Dolejškova 1402/5, 182 00 Praha 8, Czech Republic, www.it.cas.cz
1)
simek@it.cas.cz, 2) bejvl@it.cas.cz, 3) skramlik@it.cas.cz, 4) valouch@it.cas.cz
Abstract — Current-controlled voltage source
converters are widely used in grid-connected applications,
for example for ac drives with indirect frequency
converters. The structure and parameters of the PLL are
developed and proposed in order to cope with the grid
containing both the positive and the negative sequence
components, and minimize the wrong frequency transients
during phase angle steps and also in the start-up stage. The
DSC (Delayed Signal Cancellation) technique was realised.
There is also necessary to compensate the negative sequence
component in the grid voltage. The negative sequence
component of the grid voltage causes ripples of the dc
voltage in the DC link. Several sophisticated topologies of
converter current controller were developed, simulated and
tested for this purpose. Results of simulation and
experimental tests are provided to evaluate different current
control schemas and phase locked loop techniques.
Keywords — Phase Locked Loop (PLL), DSC, Current
Controller, PWM rectifier.
I. INTRODUCTION
The ac/dc rectifiers are often used in many applications,
especially in electric drives with ac motors. The rectifier
works at these drives as an input part of the indirect
frequency inverter.
In an ideal situation, the 3-phase grid voltage is harmonic,
shifted by 120° phase-by-phase, and the voltage and
current are in phase. The track of the space vector of the
3-phase voltage transformed to αβ coordinates has a form
of the circle.
In a real situation, the 3-phase grid voltage is distorted by
a negative sequence component, high-order harmonics
and by a shift between voltages and currents in the
phases, which produces a reactive power and also ripples
in the voltage on the capacitors in the DC link. The track
of the space vector of the 3-phase voltage transformed to
αβ coordinates has a deformed form.
This deformed track of the voltage space vector, with
harmonics neglected, consists of the positive and negative
superposed components. The first component is equal
with the ideal circle shape of the space vector track and is
running by frequency 50 Hz. This is so called positive
sequence component. The second component of the space
vector is running in the opposite direction with the
frequency 50 Hz and represents the negative sequence
component of the grid voltage. The second component is
called negative sequence component.
Now, our object is an analysis of the positive and
negative sequence component control of the ac current in
order to eliminate reactive power, high-order harmonics
and the ripples of the voltage in the dc link. The current
also consists of the positive and the negative sequence
components similarly like the voltage. Both components
of the current are controlled separately and
simultaneously. The positive sequence component of the
current is controlled in the positive coordinates, which
looks like the dc control. The negative sequence
component of the current is controlled in the negative
coordinates, which looks like the dc control too. Both of
these controls are realized simultaneously by separate PI
controllers. This system is very effective because it
permits the complete control by one chip and one
program without additionally SW or HW devices.
The necessary condition of a reliable operation of an
electronic power converter connected to the grid is an
effective synchronization of the control system, usually to
the positive sequence component of the grid voltage. We
present a several possibilities of the synchronization by
Phase Locked Loop (PLL) strategies in the text below.
Transactions on Electrical Engineering, Vol. 2 (2013), No. 1
11
Fig. 1: Control schema of rectifier with standard dual current controller; reproduced from [1]
From many methods published recently only those were
selected for an analysis which are suitable for three phase
systems and do not need tuning of many parameters (like
e.g. those with varying switching periods, with adaptive
parameter tuning, with many low- or high-pass filters,
etc.). These selected PLL techniques have been more or
less verified by simulations or experiments and
recommended to use not only by their authors too.
can cause dc voltage ripples. It means that the control
system based on calculation from
ea , eb , ec is not
usable for an extremely unbalanced grid.
B. Nonlinear dual current controller
A new method, which calculates current references
idqp∗
pn
idqn∗ with help of the output voltage vdq
, was proposed in
II. CURRENT CONTROLLER: INVESTIGATED AND TESTED
METHODS
A. Standard dual current controller
displays the schema of the control algorithm, which is
considered to be a standard dual current controller [1]-[2].
This control system is based on calculation of the
reference
currents
with
help
of
the
grid
voltages
ea , eb , ec . For the exactly working control
system it is necessary to compute the current references
from voltages
va , v b , vc , thus from voltages at the ac
poles of the converter, because v a , v b , v c , together with
phase currents, are responsible for an active power that
[3].
The
output
voltage
pn
vdq
is
expressed
by
pn
pn
vdq
= edq
± ωLiqdpn ,
where
pn
edq
is measured. The disadvantage of this method
consists in necessity to solve nonlinear equations, what is
very difficult and complicated.
C. Dual current controller with feedback from
PWM
This method will avoid the nonlinearity of the previous
one [4]. The nonlinearity is transformed to linearity by
use an additional feedback path for pole voltages
Transactions on Electrical Engineering, Vol. 2 (2013), No. 1
Phase error
Input v1(t)
v2(t)
12
Phase
detector
ϑe
Loop filter
(PI Controler)
ω
VCO
Fig. 2: Basic structure of closed loop PLL
(va , v b , vc ) . So, the algorithm for calculation of the
which is dissipated in filters, are used:
current references becomes simpler. The four sequence
In the first case (case 1), the dc side of the converter
supplies oscillating power to the filter, it means that the
oscillating powers are set to zero on the grid side, i.e.
components of the pole voltages
vdp , v qp , vdn , vqn , are
extracted from the space vector PWM block and fed back
to the algorithm for calculation of the current references.
Ps2in = Pc2in = 0 .
A disadvantage of the methods is that oscillating powers
that have been dissipated in the input filtering inductors
are neglected.
In the second case (case 2), the oscillating power flows
from the grid into the filter, i.e. the oscillating powers are
forced to zero at the converter terminals
and
Pcin2 = - ∆Pc2
Psin2 = - ∆Ps2 .
D. Dual current controller with calculation of
dissipated power
This method [5] comes from calculation of the power,
which is dissipated in the input inductors. The method
calculates the current references with the help of the
measured voltage e. The difference is considered between
the power at the grid side and power at the ac side of the
converter. So the regard to losses at the inductors is
assumed. But the equations for the power are still
nonlinear. The authors avoided the nonlinearity by giving
the previous patterns of the calculated reference current
to the equations for calculating the actual current
references.
So nonlinearity (multiplying unknown components of the
current with unknown components of the current) is
replaced by linearity. This is the difference between this
work and the nonlinear controller.
Two different methods for calculation of the power,
Input vabc(t)
III.
GRID SYNCHRONISATION
The PLL unit can be described by the basic structure
shown in the block diagram in Fig. 2 This PLL structure
comprises a phase detector (PD), a loop filter (LF), and a
voltage controlled oscillator (VCO). Each part of which
can be implemented in several different forms.
The block diagram in Fig. 2 shows a basic structure of the
closed loop synchronization block. The input (reference)
signal is compared with the internal (estimated) signal in
the phase detector (PD), called also phase comparator.
The phase error being the output of this block is used as
the input signal for the frequency controller (PI).
Frequency from this controller is used for the control of
the Voltage Controlled Oscillator (VCO). The output of
the VCO is compared with the input signal in the PD
block. When the input and internal signal are in the same
vsd=Vs
abc
abc→dq
dq
vsq→0
ω
PI
ϑcont
∫ dt
Fig. 3: Block structure of the SFR-PLL
ϑ
ϑ
to 0..2π
Transactions on Electrical Engineering, Vol. 2 (2013), No. 1
angular frequency and phase angle, the error signal is
zero and PLL is in steady state.
13
Voltage Vd, Vq
10000
Vq
5000
A. SFR (Synchronous Frame Reference)
A basic closed loop technique is the SFR-PLL
(Synchronous Frame Reference PLL) where the reference
frame is synchronized by the vector of the grid threephase voltage. It is the most extended technique used for
frequency and phase angle detection in three phase
systems.
The input voltage is transformed to the synchronous
reference frame. One of two synchronous components is
required to be zero (in Fig. 3 vsq). If the first component is
(nearly) equal zero the second component represent
magnitude Vs of the grid voltage vector and the angle ϑ
represents the instantaneous phase angle of this vector.
Vd
0
-5000
1.4
1.5
1.6
1.7
1.8
1
1.9
2
2.1
2.2
2.3
Vabc
4
x 10
Va
Vb
0
Vc
-1
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
error of angle (in degrees)
1
Source
SFR
0.5
0
-0.5
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
frequency
52
Under ideal grid conditions (without harmonic distortion
and negative sequence component) a high bandwidth of
the SFR-PLL feedback loop yields a fast and precise
detection of the phase and amplitude of the grid voltage
vector. In case when utility is distorted with high order
harmonics, the SFR-PLL can operate satisfactorily only if
this bandwidth is reduced.
Fig. 4 shows typical waveforms obtained by using the
SFR PLL. The upper graph shows the detected voltages
in the synchronous frame (vd, vq). The lower graph shows
the instantaneous angle error (top), and the instantaneous
detected frequency (middle). Here, the blue lines sign the
theoretically correct values. The bottom graphs in both
diagrams show the phase voltages. Between 1.5 and 2.5 s
the voltage negative sequence component of the
magnitude 10 % was added. The negative sequence
component is transferred as a second order harmonic in
the transformed voltages, and manifests itself in the
detected frequency and phase waveforms.
B. DDSFR (Double Decoupled Synchronous Frame
Reference)
In [11] the method for decoupling the positive and
negative sequence voltage components was described.
This method uses the filtered negative and positive
sequence components to eliminate (decouple) them in the
input signal. A decoupling cell is used for the
cancellation of the coupling effect between signals in the
two different frames.
Block diagram of the DDSFR-PLL is shown in Fig. 5.
The decoupling cell for decoupling signals between
Source
SFR
51
50
49
1.4
1.5
1.6
1.7
1.8
1
1.9
V
4
x 10
2
2.1
2.2
2.3
abc
V
V
0
V
-1
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
a
b
c
2.3
Fig. 4: SFR-PLL under unbalanced grid conditions. The negative
sequence component of magnitude 10 % was added between
1.5 and 2.0 s
positive and negative sequence components can be
expressed as
v*d +  vd +   cos2ϑ sin2ϑ vd − 
 * +  = v +  − 
 
vq   q  −sin2ϑ cos2ϑ vq− 
(1)
v*d −  vd −   cos ( −2ϑ) sin ( −2ϑ)  vd + 
 
 *  =  −
vq−  vq−  −sin ( −2ϑ) cos ( −2ϑ) vq+ 
The low pass filters at the outputs of the decoupling block
stop (or attenuate) the transformed negative sequence
component (it is transferred as a component with double
frequency). All the frequencies at the input that are
greater than this frequency (i.e. harmonics) are attenuated
too. But only the negative sequence component is
decoupled and quite suppressed. The PLL filter is situated
outside of the control loop. Thus, the loop bandwidth of
the PLL is not reduced.
The simulation of this type of PLL was performed with
the recommended LPF type (Butterworth of the 4th order)
and cut-off frequency value. The Fig. 6 shows transient
Transactions on Electrical Engineering, Vol. 2 (2013), No. 1
abc
dq+
vabc
v*d +
vdq +
abc
dq−
14
v*q +
Decoupling
v*d −
cells
vdq −
v*q −
LPF
LPF
Vs = vd
vd +
vq +
PI
LPF
LPF
ω
1
s
ϑ
vd −
vq −
Fig. 5: Block diagram of the DDSFR-PLL strategy
response after applying an unsymmetrical voltage
component.
Positive sequence
10000
V q+
5000
V d+
0
-5000
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
Negative sequence
C. DSC (Delayed Signal Cancellations)
The DSC (Delayed Signal Cancellation) strategy
represents an effective and robust method for the
detection of the positive and negative sequence
components of the voltage in the three-phase system. The
positive sequence vector appears as a dc component in
the synchronous reference frame.
500
V q0
V d-
-500
-1000
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
V abc
4
1
x 10
Va
0.5
Vb
0
+
vαβ
( t ) = 0.5 ( vαβ ( t ) + jvαβ ( t − T4 ) )
Vc
-0.5
-1
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
The voltage vector in a stationary α-β reference frame is
delayed. This technique is based on a combination of the
positive- and negative-sequence components with a time
delay of one quarter of a period (5 ms at 50 Hz).
2.3
(2)
−
vαβ
( t ) = 0.5 ( vαβ ( t ) − jvαβ ( t − T4 ) )
error of angle (in degrees)
0.6
Source
DDSFR
0.4
0.2
D. PLL based on the pq theory [14]
0
-0.2
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
frequency
Source
DDSFR
50.65
50.6
The phase detector operation is based on the product of
the space vectors v1(t) and v2(t). Its output can be
obtained from
50.55
50.5
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
x 10
e
j ( Φ1 −Φ 2 )
(3)
where the asterisk (*) denotes the complex conjugate
quantity. Alternatively, the phase error signal can be
expressed in rectangular form as
Va
0.5
Vb
0
Vc
-0.5
-1
1.4
j (ω1 −ω2 )
V abc
4
1
vd ( t ) = v1 ( t ) ⋅ v2 ( t ) = V1V2 e
*
50.45
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
Fig. 6: Detection of positive and negative sequence in the
synchronous frames (dq+ and dq-) with DDSFR-PLL
vd ( t ) = ( v1α v2α + v1β v2 β ) + j ( v1β v2α − v1α v2 β ) (4)
It is evident from
(4) that the real and imaginary
components of vd(t) have, respectively, the same form as
the p and q power components from Akagi’s
instantaneous power theory.
Transactions on Electrical Engineering, Vol. 2 (2013), No. 1
fiα
vabc
abc
cos(ϑ)
vα
PI
controller
fp
αβ
15
vβ
fiβ
ϑ
ω
∫ dt
sin(ϑ)
Fig. 7: PLL based on the pq theory
Two different approaches can be adopted: if the real part
of vd(t) is used as the feedback error signal, then we have
the so called p-type PLL system. Using the imaginary
part of vd(t) yields the so called q-PLL.
(stationary α-β and synchronous d-q). The extracted
positive sequence voltage component is the input to an
SFR-PLL for detecting the frequency and the angle of the
desired voltage vector.
Now considering that ω1=ω2 = ω0 (i.e. the p-type PLL is
nearly locked at the centre frequency), then the phase
error signal given by (3) can be simplified to
It is possible to obtain the symmetrical phasor
components (s+, s- and s0) of a three-phase signal from
vd = VV
1 2con (ϑ1 − ϑ2 )
 S%+ 
1 1∠120° 1∠ − 120°   S%a 
%  1
 % 
 S −  = 3 1 1∠ − 120° 1∠120°   S b 
 S%0 
1
  S%c 
1
1
 
(5)
For small deviations it can be approximated linearly by
vd ( t ) ≈ K dϑe ( t )
(6)
(6)
The negative and positive components can be extracted in
the abc system by
where ϑe is the phase error and Kd = V1V2.
Block diagram is showed in the Fig. 7. The resulting
quantity can also be interpreted as being analogous to the
instantaneous real power according to Akagi’s pq theory.
E. Simple mathematical transformations for
canceling some harmonics [15]
This is the next method for elimination of the negative
sequence component and most harmonics. The method is
based on different ways of obtaining the positive and
negative sequence components of the grid voltage, by
applying the symmetric component theory to the voltage
vector transformed into different reference frames
vabc
αβ
S%a− 
1∠60° 1∠− 60° S%a 
 −1
 %−  1 
 
−1
1∠60°  S%b  (8)
Sb  = 3 1∠− 60°
S%c− 
 1∠60° 1∠− 60°
−1  S%c 
 
 S%a+ 
1∠− 60° 1∠60°  S%a 
 −1
 %+  1 
 
−1
1∠− 60° S%b  (9)
 Sb  = 3  1∠60°
 S%c+ 
1∠− 60° 1∠60°
−1  S%c 
 
The operations (8) and (9) can be written in different
ways for obtaining the same response if the phase signals
contain only the fundamental frequency components.
vq
αβ
abc
Cαβ
Dαβ
dq
(7)
Aαβ
Bαβ
Fig. 8: Block diagram of the PLL which uses the mathematical
transformations
MDC
ϑ
ω
PI
∫ dt
Transactions on Electrical Engineering, Vol. 2 (2013), No. 1
16
However, the harmonics presented in the original signals
are differently modified by each of such operations.
the corresponding values in degrees. The negative
advance is used to indicate delayed instantaneous signal.
The Eq. (8) can be rewritten as (in the instantaneous
values)
The formulas (10) - Chyba! Nenalezen zdroj odkazů.
can be used to improve the operation under harmonics of
the SFR-PLL after the transformation to the stationary αβ frame [15] (Fig. 8). Most of the harmonics has been
suppressed (all odd except 12n+1, (n is an integer)) or
  sa 
 sa− 
 sa 60 
 sa −60  
1  
 −




 sb  = − 3  A1  sb  + A2  sb 60  + A3  sb − 60   (10)
 s 
 sc− 
 sc 60 
 sc − 60  
 




  c
AB
1
0.8

 sa− 
 sa 
 sa −90  

1
 −
 


 sb  = 3  − B1  sb  + B2  sb −90  

 sc− 
 sc 
 sc −90  
 
 



0.6
(11)
(11)
0.4
0.2
0
-15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1
The Eq. (9) can be rewritten as (in the instantaneous
values)
0 1
2
3
4
5
6 7
8
9 10 11 12 13 14 15
Fig. 9: Gain of the operation A and B in cascade
  sa 
 sa+ 
 sa −60 
 sa 60  
1  
 +


 
 sb  = − 3  C1  sb  + C2  sb −60  + C3  sb 60   (12)
 s 
 sc+ 
 sc −60 
 sc 60  
 


 
  c
CD
1
0.8
0.6
0.4
0.2

 sa+ 
 sa 
 sa 90  

1
 +
 


 sb  = 3  − D1  sb  + D2  sb 90  

 sc+ 
 sc 
 sc 90  
 
 



0
-15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2
3 4 5 6 7 8
9 10 11 12 13 14 15
(13)
Fig. 10: Gain of the operation C and D in cascade
attenuated.
where the matrixes
 −1 0 0 
A1 = C1 =  0 −1 0 
 0 0 −1
0 1 0 
A2 = C2 = 0 0 1 
1 0 0 
0 0 1 
A3 = C3 = 1 0 0 
0 1 0 
1
 −1 12
2 

1
1 
B1 = D1 =  2 −1 2 
1
 12
−1
2
 0

B2 = D2 =  − 23
 3
 2
3
2
0
−
3
2


3
2 

0 
−
Due to the synchronous d-q frame transformation the
harmonic order of a component in the input signal is
decreased. Then, even harmonics become odd and vice
versa. The signals in the synchronous d-q reference frame
go through the operation A and B in cascade. The gain of
this operation is shown in Fig. 9. Then the odd harmonics
(even harmonics in the original signal) are eliminated.
The gain of the operation A and B in the cascade is
shown in Fig. 10.
The eleventh negative and thirteenth positive (and all
other harmonics 12n+1) get through without attenuation,
as well as the fundamental harmonic. This harmonic
cannot be suppressed by use of this method.
3
2
(14)
The subscripts 60 and 90 are used to indicate
instantaneous signals advanced from the original ones by
F. PLL with moving average value
The integral of the voltage of any harmonic frequency in
the full period of the fundamental frequency is zero. This
mathematical knowledge is used in the Frequency
Transactions on Electrical Engineering, Vol. 2 (2013), No. 1
Input vabc(t)
17
vsd=Vs
abc
abc→dq
dq
vsq
AVG
ω
PI
∫ dt
ϑ
Fig. 11: Block structure of the SFR-PLL
Fig. 12: Dip response under single current controller in comparison to standard dual current controller; reproduced from [1]
Variable Average PLL (FVAVG-PLL). This technique is
capable to suppress all harmonics components (Fig. 11).
IV.
SIMULATION AND EXPERIMENTAL RESULTS
A. Standard dual current controller
The 50 % dip has been simulated in order to test the
effectiveness of the dc controller under the condition of
an unbalanced voltage [1]. The current of the dc-link load
is constant 0.5 p.u. Fig. 12 displays response of the output
dc voltage to the described dip, where the single current
controller and standard dual current controller have been
used. The dip starts at 20ms and ends at 180ms. It is
obvious that the dc voltage ripple is almost zero under the
dual controller. For the single current controller system,
the dc-voltage ripple oscillates with twice the grid
frequency and the amplitude of the ripple is 4 %. So,
possibilities of the single current controller system are
limited in the presence of negative sequence components.
Fig. 13: Simulation waveforms for the single controller under
unbalance; reproduced from [3]
Transactions on Electrical Engineering, Vol. 2 (2013), No. 1
18
B. Nonlinear dual current controller
This type of the dual current controller was tested under
Fig. 16: Simulation waveforms of the dual current controller with
feedback from PWM controller with a compensation for the 15 %
one phase unbalance; reproduced from [4]
Fig. 14: Simulation waveforms for the nonlinear dual current
controller under unbalance; reproduced from [3]
conditions of 15 % decrease of the voltage amplitude in
one phase [5]. This type of unbalance appears often in a
weak ac system.
The simulation results are displayed in Figs. 13, 14. The
figures display waveforms of the dc voltage vdc, phase
current ia and grid voltage ea.
Fig. 13 displays results if the simple single PI controller
without any compensation of the unbalance in the control
program is used. Fig. 14 displays results of the dual
current controller.
Fig. 17: Grid current (top) and dc voltage (bottom) with single current
controller; reproduced from [5]
It is obvious that the output voltage vdc has a strong ripple
in its waveform in Fig. 13. The output voltage vdc has any
ripple in its waveform in Fig. 14.
C. Dual current controller with feedback from
PWM
The dual current controller with the feedback from PWM
was tested under conditions of 15 % decrease of the
voltage amplitude in one phase [4].
Fig. 15: Simulation waveforms of the single controller without a
compensation for the 15 % one phase unbalance; reproduced
from [4]
Fig. 15 and Fig. 16 display simulation the waveforms of
the line voltage wave form in phase a (ea), line current in
phase a (ia) and output dc voltage (vdc). Fig. 15 displays
results of the conventional single PI controller use
without unbalance compensation. Fig. 16 displays results
of the dual current controller use. We can see that the
dual current controller provides much lower ripple of the
vdc than the conventional controller.
Transactions on Electrical Engineering, Vol. 2 (2013), No. 1
19
1
x 10
4
v alpha, sine, cosine
v alpha
sine
cosine
0
-1
0.3
0.31
0.32
0.33
0.34
0.35
theta
0.36
0.37
0.38
0.39
10
0.4
theta
5
0
0.3
1
0.31
x 10
0.32
0.33
4
0.34
0.35
0.36
v d, v q, v+ d, v+ q
0.37
0.38
0.39
0.4
vd
v+ d
vq
v+ q
0
-1
0.3
0.31
0.32
0.33
0.34
0.35
0.36
Time(s)
0.37
0.38
0.39
0.4
Fig. 20: Waveforms of DSC-PLL after unbalance is added
to input voltage (vd, vq – input voltages, v+d, v+q –
detected positive sequence)
Fig.18: Grid current (top) and dc voltage (bottom) with dual current
controller with calculation of dissipated power in method 1; reproduced
from [5]
It is obvious that the use of this algorithm results in
quality current references. On the other side, the dc side
supplies the oscillating powers and therefore the dc ripple
is about to 20 %.
Fig. 19 displays waveforms of the grid currents and
output dc voltage for the dual current controller algorithm
of the method 2. With the oscillating powers supplied by
the grid, the dc voltage is smoothed out, apart from the
transients at the beginning and end of the dip.
The currents are almost the same in magnitude in both
cases, but they are more smoothed in the case 2.
Fig. 19: Grid current (top) and dc voltage (bottom) with dual
current controller with calculation of dissipated power in
method 2; reproduced from [5]
D. Dual current controller with calclatiton of
dissipated power
Several simulations were realized in order to test the
controller [5]. There was a 40 % dip in the phases B and
C.
Fig. 17 displays waveforms of the grid currents and
output dc voltage for the single current controller. The
unbalance of the grid voltage causes the ripple in the
output dc voltage of about 6.5 %.
Fig. 18 displays waveforms of the grid currents and
output dc voltage for the dual current controller
algorithm. The dual current controller algorithm of the
method 1 was used here.
Fig. 21: Measured time responses of DSC-PLL after changing grid
voltage in unbalanced form: a) upper part: grid voltage component va
(1000 V/div), sinΘ, cosΘ; b) middle part: angle Θ (π/div); c) lower part:
grid voltage components vd, vq (250 V/div) – time scale 10 ms/div
E. Phase Locked Loop strategies
All proposed PLL strategies were simulated with
different parameters and by several voltage distortions.
Fig. 20 shows the response of the DSC-PLL to the
unsymmetrical voltage (the magnitude of the voltage in
the phase a was rapidly decreased). In Fig. 20, lower part,
Transactions on Electrical Engineering, Vol. 2 (2013), No. 1
20
Frequency
Frequency
50.4
50.15
Source
DSC
DDSFR
50.2
Source
FVAVG
SFR
50.1
50.05
50
50
49.8
49.95
49.6
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
1.4
1.5
1.6
Angle Error (in Degrees)
1
0.5
0.5
0
0
-0.5
-0.5
1.5
1.6
1.7
4
1
1.8
1.9
2
2.1
-1
1.4
2.2
1.5
1.6
1.7
4
Voltage
x 10
1.8
1.9
2
2.1
2.2
2.1
2.2
Angle Error (in Degrees)
1
-1
1.4
1.7
1
1.8
1.9
2
Voltage
x 10
Va
0.5
Vb
Vc
0
-0.5
-1
1.4
Va
0.5
Vb
Vc
0
-0.5
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
-1
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
Fig.22: Waveforms obtained by applying DSC-PLL, DDSFR-PLL, FVAVG-PLL, SFR-PLL strategies when unbalance is added to input
voltage
two pairs of the d, q grid voltage components are
+
d
depicted: vd, vq of the real grid voltage and v ,
+
q
v of the
extracted positive symmetrical voltage sequence
component only, which are used in the DSC-SPLL
algorithm to synchronize the controller to the grid.
The DSC-PLL method was adopted as the most suitable
for a practical realisation.
Fig. 21 presents captured time responses of the DSC-PLL
variables under the same conditions as those in Fig. 20.
High frequency disturbances at the instant of a voltage
system change result from the switch process in the
programmable power source. Nevertheless, even by this
dramatic voltage change, the synchronization was
reached in circa half of the fundamental period (that is,
+
the components v d ,
v q+
V. CONCLUSION
It has been introduced that the unbalanced input voltage
causes wrong work of the rectifier. So the unbalance must
be compensated. These compensations are really very
important for a good function of the PWM rectifier. The
compensation method must be tested in different nonstandard states and also in transient processes. Therefore,
a lot of efforts have been made to propose a control
schema, which would make possible to compensate the
input voltage unbalance reliably.
In the second part of the paper an overview of different
synchronizations techniques suitable for the three phase
PWM rectifiers were presented. Most of the techniques
were simulated too. The DSC-PLL technique was
realized in the control system with the DSP.
were again constant).
Fig. 22 shows the responses of different PLL’s by an
unsymmetrical input voltage. The DSC-PLL, DDSFRPLL, FVAVG-PLL, SFR-PLL strategies were simulated
and compared. The responses of the estimated frequency,
angle error, and three-phase voltages are presented. The
negative sequence component was added between
1.5 and 2.0 s.
ACKNOWLEDGEMENT
With institutional support RVO//:61388998.
Financial support of the Ministry of Industry and Trade of
the Czech Republic, through grant number FR-TI1/330, is
highly acknowledged.
Transactions on Electrical Engineering, Vol. 2 (2013), No. 1
21
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[1]
[2]
[3]
[4]
[5]
[6]
[7]
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grid-connected voltage source converter under unbalanced
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operating conditions”. Conference record of the industry
applications conference, 2002. 37th IAS annual meeting, vol. 2,
13th – 18th October 2002. Pages 1189 – 1196.
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IEEE Power electronics specialists conference.
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performance of voltage source converter under unbalanced
voltage dips”. IEEE 35th annual power specialists conference
(PESC´04). Aachen, Germany. 20-25 June 2004. Pages: 1163 –
1168.
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Burgos, Rolando P. Boroyevich, Dushan "Decoupled Double
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The contribution was presented on the conference ELEN 2012, PRAGUE, CZECH REPUBLIC
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