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CDA 4203 Sec 001 Spring 2015
Computer System Design
Instructor: Dr. Srinivas Katkoori
Homework 4 – ADCs, DACs, and USB
ADCs and DACs
1. (5 pts.) Briefly describe the three main steps implemented in an Analog-to-Digital Converter.
a. Sampling: It is where is generated the conversion of a continuous-time signal into a discretetime signal by taking samples at regular intervals
xa(nT) = x(n) where T is the sampling interval
b. Quantization: It is where is generated the conversion of discrete-time continuous-valued signal
into a discrete time, discrete values (digital) signal. The value is chosen from a finite set of
possible values. The difference between unquantized sample x(n) and xq(n) is known as
quantization error.
c. Coding: It is where each discrete value xq(n) is represented by a b-bit binary sequence
2. (10 pts.) Given an analog output signal whose voltage should range from 0 to 10V, and an 8-bit
digital encoding, provide the encodings for the following desired voltages: (a) 0V, (b) 1V, (c)
5.33V, (d) 10V, what is the resolution of the conversion?
n = 8, 2n – 1 = 255
Vmin = 0, Vmax = 10
a) 0V
0 / 10 = d / 255
d=0
00000000
b) 1V
1 / 10 = d / 255
d = 25.5 ≌ 25
00011001
c) 5.33V
5.33 / 10 = d / 255
d = 135.9 ≌ 136
10001000
d) 10V
10 / 10 = d / 255
d = 255
11111111
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3. (10 pts.) Given an analog input signal whose voltage ranges from 0 to 5V, and an 8-bit digital
encoding, calculate the correct encoding for 3.5V, and then trace the successive-approximation
approach (i.e., list all the guessed encodings in the correct order) to find the correct encoding.
Vin = 3.5V Vref = 5V
3.5/5 = d/255
d = 178.5 ≅ 179
10110011
i=7 SAR[7] = 1; d=128; V = 5 * 128/255 = 2.5 < 3.5
10000000
i=6 SAR[6] = 1; d=192; V = 5 * 192/255 = 3.76 > 3.5
10000000
i=5 SAR[5] = 1; d=160; V = 5 * 160/255 = 3.13 < 3.5
10100000
i=4 SAR[4] = 1; d=176; V = 5 * 176/255 = 3.45 < 3.5
10110000
i=3 SAR[3] = 1; d=184; V = 5 * 184/255 = 3.60 > 3.5
10110000
i=2 SAR[2] = 1; d=180; V = 5 * 180/255 = 3.52 > 3.5
10110000
i=1 SAR[1] = 1; d=178; V = 5 * 178/255 = 3.49 < 3.5
10110010
i=0 SAR[0] = 1; d=179; V = 5 * 179/255 = 3.50 < 3.5
10110011
4. (5 pts.) Sketch the successive approximation ADC circuit and explain how it works.
DAC = digital-to-analog converter
EOC = end of conversion
SAR = successive approximation register
S/H = sample and hold circuit
Vin = input voltage
Vref = reference voltage
The successive approximation Analog to digital converter circuit typically consists of four chief
subcircuits:
1. A sample and hold circuit to acquire the input voltage (Vin).
2. An analog voltage comparator that compares Vin to the output of the internal DAC and
outputs the result of the comparison to the successive approximation register (SAR).
3. A successive approximation register subcircuit designed to supply an approximate digital
code of Vin to the internal DAC.
4. An internal reference DAC that, for comparison with VREF, supplies the comparator with
an analog voltage equal to the digital code output of the SARin.
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It is a type of analog to digital converter that converts a continuous analog waveform into a
discrete digital representation via a binary search through all possible quantization levels before finally
converging upon a digital output for each conversion. It starts by connecting the analog input to the SHA,
which acquires the input voltage. When the switch opens, the comparator determines whether the analog
input is greater than or less than the DAC voltage. To start, the most significant bit (MSB) is on, setting the
DAC output voltage to midscale. After the comparator output has settled, the successive-approximation
register turns off the MSB if the DAC output was larger than the analog input, or keeps it on if the output
was smaller. The process repeats with the next most significant bit, turning it off if the comparator
determines that the DAC output is larger than the analog input, or keeping it on if the output was smaller.
This binary search continues until every bit in the register is tested. The resulting DAC input is a digital
approximation of the sampled input voltage, and is output by the ADC at the end of the conversion.
5. (5 pts.) What are the main advantages/disadvantages on an R-2R DAC?
Advantages:
 Matching Resistors is easy
 By selecting low values of R (2.5kΩ - 10 kΩ), we can achieve good DAC response time
 Op-amp always sees a constant impedance at its input leading to better accuracy
 Basis of many commercial DACs
Disadvantages
 Relatively low output impedance
 Total device emitter area is not practical for high resolution DACs
 INL/DNL error due to amplifier offset
6. (5 pts.) What is Nyquist’s theorem? What problem do we encounter if we do not meet Nyquist’s
sampling rate?
The Nyquist’s theorem is a principle that engineers follow in the digitization of analog signals. For
analog-to-digital conversion (ADC) to result in a faithful reproduction of the signal, called samples, of
the analog waveform must be taken frequently. The number of samples per second is called the sampling
rate or sampling frequency.
The Nyquit’s theorem says that if the highest frequency contained in an analog signal xa(t) is Fmax =
B and the signal is sampled at a rate Fs > 2 Fmax then xa(t) can be exactly recovered from its sample
values using interpolation. Thus, we need to sample two times faster than the maximum frequency
component. If we do not meet this requirement, then, we will lose signal information.
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(Extra credit 20 pts) USB 2.0 Protocol
7. (5 pts.) What are the different speeds supported by USB 2.0 protocol? For each speed, (a)
identify the supported data transfer rate; (b) give an example of a peripheral.
The different speeds supported by USB 2.0 protocol are:
 Low-Speed USB (LS-USB) with a 1.5 Mb/s
o It can transfer application data up to 187.5 KB/s (1.5 Mb/s)
o However, 8 byte data transfer every 10 ms = 800 Bytes/second only
 Full-Speed USB (FS-USB) with 12 Mb/s
o It can transfer data up to 1.5 MB/s (12 Mb/s)
o However, 1.5 MB/s is the total bus bandwidth
 Must be shared among peripherals
 Protocol overhead
 Protocol restrictions
 Realistic raw data throughput to a single peripheral is ~1.0 MB/s
 Only 64KB/s in some cases
 High speed (HS-USB) with 480 Mb/s
o It can transfer data up to 480 Mb/s
Example of a peripheral:
 Keyboard
 Speaker
 USB
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8. (5 pts.) What are different types of Tokens? For each token type, briefly explain its purpose.
SETUP Token: indicates beginning of control transfer. It inform the target device that the host wants to
send data - used to being control transfer. It is used to begin control transfers. Token packets identify the
targeted endpoint and the purpose of the transfer of information.
OUT Token: inform the target device that the host wants to send information. Informs the USB device
that the host wishes to transmit information.
IN Token: informs the target device that the host wishes to read information.
9. (5 pts.) What are the four types of data transfer? Compare them in terms of polling interval,
priority, and delivery guarantees.
The four types of data transfer are:
 Insert
o Fixed Periodic (polling interval)
o Priority high
o Guarantees 64 Bytes/Period data Integrity
 Isochronous
o Fixed Periodic (polling interval)
o Priority high
o Guarantees 1023 Bytes/Period
 Bulk
o Variable Uses free bandwidth (polling interval)
o Priority low
o Guarantees Data Integrity
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 Control
o Variable (polling interval)
o Medium
o Guarantees some Bandwidth, data Integrity
10. (5 pts.) How is the plug-n-play feature work to identify full-speed and low-speed peripherals?
It is one with a specification that facilitates the discovery of a hardware component in a
system without the need for physical device configuration or user intervention in resolving
resource conflicts. In a plug-n-play feature a, non-return to zero, inverted, data passes through the
devices in either Isochronous or Asynchronous fashion by pulling either D+ or D- line high to 3.3
v.
Two methods:
1. Auto-Detection - Full speed identification D + line pull-up with a V usb 3.3 V and 1.5 kOhm
±5%.
2. Auto-Configuration - Low speed identification D - line pull-up with a V usb 3.3 V and 1.5 kOhm
±5%.
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