Download VLSI Design of Low Power ALU Using Optimized Barrel Shifter

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International Journal of VLSI and Embedded Systems-IJVES
ISSN: 2249 – 6556
VLSI Design of Low Power ALU Using Optimized Barrel Shifter
MEETU MEHRISHI1, S. K. LENKA2
1
Electronics and Communication, MITS University, Lakshmangarh, India
2
Information Technology, MITS University, Lakshmangarh, India
1
[email protected], [email protected]
ABSTRACT
The purpose of this work is to design, implement and experimentally verify an Arithmetic Logic Unit (ALU)
using Low Power Barrel Shifter. Barrel shifter is most widely used in ALU to perform fast shifting operations.
This work evaluates the performance of ALU with optimized design of barrel shifter in 90nm and 65nm CMOS
process technology. Dynamic logic with no precharge pulse propagation problem and SVL circuit techniques
for low leakage power are employed to optimize shifter unit of ALU for low power consumption. At first, the
circuits were simulated with shifter modules without applying the SVL circuit. And secondly, SVL circuit was
incorporated in the shifter modules for simulation. Measurement results validate the proposed concept and
verify that SVL technique based shifter results in lowering the power consumed in ALU.
Keywords: Dynamic Logic, Leakage Power, Barrel Shifter, Self Controllable Voltage Level Circuit
[1] INTRODUCTION
ALU is one of the main components of microprocessor. They use fast dynamic logic circuits and have carefully
optimized structures. Its power consumption accounts for a significant portion of total power consumption of
data path [1]. ALU also contribute to one of the highest power-density locations on the processor, as it is
clocked at the highest speed and is kept busy most of the time resulting in thermal hotspots and sharp
temperature gradients within the execution core. Therefore, this strongly motivates energy-efficient ALU
designs that satisfy the high-performance requirements, while reducing peak and average power dissipation [2,
3]. ALU is a combinational circuit that performs arithmetic and logical micro-operations on a pair of n bit
operands e.g. A [0:7] B [0:7] for 8 bits. The typical internal structure of a 32 bit ALU is shown in Fig.1. The
architecture can be modified similarly for lower bits. This work is divided into following sections: Section II
gives description of various units and operations of ALU, Section III briefly presents the designing of barrel
shifter, Section IV presents the proposed barrel shifter design using SVL logic, Section V presents the
simulation results and performance analysis of barrel shifter and ALU, finally the work is concluded in Section
VI.
2. ARITHMETIC LOGIC UNIT
2.1
Arithmetic Unit
Employing fast and efficient adders in arithmetic logic unit will aid in the design of low power high
performance system. Other instructions such as subtraction and multiplication also employ addition in their
operations, and their underlying hardware is similar if not identical to addition hardware. Various adder families
have been proposed in the past to trade off speed, power and area for possible use in ALUs. The performance
criticality of the ALU demands a dynamic adder implementation [3].Dynamic logic family of adders are the
most efficient in terms of transistor count, speed and overall power dissipation. This work covers the design of 1
bit adder using TSPC and PDB logic to avoid the problem of precharge pulse propagation (discussed in section
3) persistent in dynamic logics. Adder is also used for the implementation of subtractor unit in the ALU. This
reuses the current hardware and saves area.
Fig.1 Internal Architecture of ALU
2.2
Logic Unit
ALU can perform various logic operations like NOT, AND, NAND, NOR, XOR, XNOR etc. For these
instructions a bit-slice design is followed where the logic for only one bit of the output needs to be created, and
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then arrayed out to the width of the ALU (in this work, 8 bits). The bit-slice for this design contains three gates,
the AND, OR, XOR. The logic gates are implemented using dynamic logic (TSPC and PDB logic). Design of a
8 bit ALU formed from cascades of 1 bit ALU is shown in Fig.2 [4].
2.3
Shifter Unit
The Barrel shifter is the circuit block in the processor that shifts the data by specified number of bits. The shifter
is designed to shift data bits logically and arithmetically either left or right. In logical left shift, the barrel shifter
will shift the data bits by specified number of bits to more significant positions and the result has lower
significant bits that are filled with zeros. In logical right shift, the barrel shifter will shift the data bits by
specified number of bits to lower significant bits and the result has higher significant bits that are filled with
zeros. The main circuit block for the barrel shifter is build based on the multiplexer circuit. When implementing
these shifters, it is difficult to include them in the bit-slice. The shifter for the ALU is implemented with a left
shifter (Fig.3), and contains a row of 2-to-1 multiplexers. Since ALU in this work is optimized using efficient
low power designing of barrel shifter, implementation of barrel shifter is discussed in section 3.
Fig.2 8 bit ALU by cascading 1 bit ALU
2.4
Low Power ALU
The different circuit techniques exist to lower the ALU leakage power consumption When technology is scaled
from 130nm to 65nm technology, there is a 27x increase in the standby mode leakage power (~30% gate
leakage) [5]. Reducing the power consumption of the ALU of high-end processors is important not only because
they consume a significant percentage of processor energy, but also because they are one of the busiest
component in the processor. As a result they dissipate a lot of dynamic energy. This is aggravated by the
exponential dependence of leakage on the temperature, and ALUs also become a site of high leakage. The total
leakage of the ALU is, IS,T=N.IS,i where N= number of transistors in the ALU I S,i= sub threshold leakage of gate
i which is a function of gate length L and threshold voltage V [2]. Similarly, the dynamic power of the ALU as
ID=α.Ceff.Vdd2.f ,where α is the switching factor, Ceff. is the total effective capacitance, Vdd is the supply voltage,
and f is the frequency of operation.
3. BARREL SHIFTER
Barrel Shifter contains repeated blocks of 2x1 multiplexer and each multiplexer block is implemented using
TSPC and PDB dynamic logic. Such logic styles are efficient in reducing power consumption as they avoid
precharge pulse propagation. The voltage at the output of the dynamic circuit is stored on a parasitic
capacitance, which is typically buffered before it is sent to the next stage. This temporary voltage is affected not
only by charge sharing of the internal parasitic capacitances but also by the consequent dynamic circuit.
Normally, a buffer at the output of the dynamic logic is required to drive the next stage. Since the output of the
dynamic gate is sampled on parasitic capacitances, periodic precharge phases of the output node are required.
Additionally, these precharge pulses introduce extra noise in the gate and the propagation of these pulses
through the static buffer result in extra power consumption [6]. Fig. 3 [7] shows the block diagram of a 3-stage
barrel shifter with inputs x0-x7 and output z0-z7 (left shifter), and each row represents a stage. It consists of 2x1
multiplexers arranged into three rows with 8 multiplexers per row. Each row of multiplexer has common select
line where s0 feeds the first row, s1 second and s2 third. A 1 in the first row (s0=1) represents a shift of one bit
to the left. When s1=1 data is shifted by 2 bits, when s2=1 data is shifted by 4 bits .When any of the shift control
bits are zero, data is passed unchanged through the row of multiplexers to the next row [8-10]. The
implementation of multiplexers for barrel shifter is shown in Fig. 4 and Fig. 5.
3.1
Multiplexer Using TSPC Dynamic Logic
The first single-phase clock policy was only introduced by Ji-Renet al. called the true single-phase-clock
(TSPC). It overcomes the problem of precharge pulse propagation using NC2MOS or PC2MOS, as shown in
Fig.4, but at the expense of an extra transistor as compared to a domino gate. In this gate, the dynamic node Z is
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precharged high and M9 is disabled. As a result, the output Out holds its previous value. This circuit requires 3
clock transistor and it increase the load capacitance of the clock signal and thus the power consumption.
Fig. 3 An 8 bit Left Barrel Shifter
Fig.4 2x1 multiplexer using TSPC dynamic logic
3.2
Multiplexer Using PDB Logic
Using this pseudo dynamic structure (PDB), the precharge pulse is blocked at the input of the buffer and is
prevented from being propagated to the output of the dynamic gate. As a consequence, the power typically
consumed in the buffer during the precharge phase is saved. Additionally, compared to TSPC-based dynamic
logic, in this logic the clock transistor count is reduced from 3 to 2. As a result, the power consumption is
significantly reduced due to lower load capacitance on the clock bus. In this circuit the source of output buffer
transistor M8 is connected to node N instead of Gnd as shown in Fig.5. Using such a circuit topology, the value
at node Z cannot propagate to the output Out during the precharge phase of the gate since during this phase, the
evaluation transistor M6 is turned off [6].
Fig.5 2x1 multiplexer using PDB dynamic logic
4. PROPOSED BARREL SHIFTER USING SVL LOGIC
A significant portion of the total power consumption in high performance digital circuits in deep submicron
regime is mainly due to leakage power. Static or leakage power makes up to 50% of the total power
consumption in today’s high performance microprocessors [11]. Leakage power dissipation is the power
dissipated by the circuit when it is in sleep mode or standby mode [12]. Leakage power is given by: P leak= Ileak *
Vdd. The dominant source of leakage power is sub-threshold leakage current given by the following equation
[13]:
(1)
And
(2)
Where is the electron/hole mobility, Cox is the gate oxide capacitance, W and L are width and length of the
channel respectively, Vth is the threshold voltage, m is the sub-threshold swing co-efficient, vT is the thermal
voltage, Vgs is the transistor gate to source voltage and Vds is the drain to source voltage. One of the efficient
techniques to reduce standby leakage power is self controllable voltage level circuit technique. The present work
describes such an analysis and shows that use of SVL switch for reducing supply voltage yields the maximum
reduction in leakage currents especially when the pre-charge transistors are put in cut-off state during the standby mode. Self- controllable switch can be used either at the upper end of the cell to reduce supply voltage
(USVL technique) or at the lower end of the cell to raise the voltage of the ground node (LSVL technique) or in
the form of combination of both.
4.1
SVL Circuit
The barrier of a short-channel device reduces with an increase in the drain voltage, which in turn increases the
sub-threshold current due to lower threshold voltage. However with the SVL technique , such as type 3 SVL
circuit shown in Figure 6 ,the supply voltages VL and Vs increase the height of the barrier close to the source of
the OFF nMOS and pMOS transistors, thus drain induced barrier lowering (DIBL) effect is reduced.
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Fig. 6 Type 3 SVL circuit
Fig.7 Proposed 8 bit left barrel shifter
Consequently, the threshold voltage of nMOS is increased (e.g for type 1 SVL circuit) and thus sub- threshold
leakage current decreases, so leakage power is minimized while the data is retained [14]. Three types of SVL
circuit have been developed in the literature i.e Type 1 or upper SVL circuit, Type 2 or lower SVL circuit, Type
3 or Upper and Lower SVL circuit. This work compares the type 3 SVL circuit technique based barrel sifter
with barrel shifter without SVL technique. Type 3 SVL circuit is used to provide lower Vdd and higher Vss to
the load circuit in standby mode. The output voltages VL and VS of type 3 SVL Circuit is given by VL=VddVn and Vs=Vp Thus, the DIBL effect on nMOS in the standby inverter is further decreased, since
. The BGB effect due to Vsub,n also occurs in the nMOS thus sub-threshold leakage
current is further reduced. A 8 bit barrel shifter incorporating a single type 3 SVL circuit with m of 4 was
designed at both 90nm and 65 nm CMOS technology. Architecture of proposed barrel shifter is shown in Fig.7
above.
4.2
Advantages of SVL Circuit
While the load circuits are in the active mode, the SVL circuit supplies the maximum drain–source voltages Vds
to the “on MOSs” through “on SWs.” Thus, the load circuits can operate quickly. On the other hand, when the
load circuits are in standby mode, it supplies slightly lower VL and slightly higher VS to MOSFETs through
“weakly on SWs”. Thus, the SVL circuit not only retains data (consequently, it can be applied to memories and
flip-flops) but also produces high noise immunity with minimal overheads in terms of silicon area. Furthermore,
the Vth increases and, consequently, sub-threshold current of the “off MOSs” decrease, so standby leakage
power is greatly reduced.
5. SIMULATION RESULTS AND PERFORMANCE ANALYSIS
All the circuits are simulated on Tanner EDA tool at 90nm and 65nm CMOS technology at 1v and 0.7v
respectively. The ALU is designed at the transistor level for performing 8 bit operation and performs the
following operations, Addition/Subtract, logical operations like XOR, AND, OR and left shift operation. The
final output stage consists of 2x1 multiplexer for selecting the final output.
5.1
Power Analysis for Barrel Shifter
Table 1 summarizes the results of power consumed by 8 bit proposed left barrel shifter incorporating Type 3
SVL circuit with m of 4 as a function of Vdd for 90 nm and 65nm CMOS technology at 1v and 0.7v
respectively. Since Type 3 SVL circuit supplies lower VL and higher Vs to barrel shifter in standby mode, the
power consumption of proposed barrel shifter is lower than other two shifter designs. This is due to the fact that
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it combines the advantage of no precharge pulse propagation by using PDB logic and lower leakage power by
using SVL low power technique. The power consumed for the TSPC logic based shifter circuit is much larger as
compared to PDB dynamic logic based shifter due to higher clock loading.
Table 1. Power comparison for different 8 bit barrel shifter as a function of supply voltage (Vdd)
Vdd(volts)
1v(90nm)
0.7v(65nm)
Power(10-5 Watt)
TSPC logic based shifter PDB based shifter
2.13
1.74
0.98
0.75
Proposed Shifter
1.41
0.61
Fig.8 shows the power plot for different shifter circuits. As it can be seen from the graph, for 65nm, proposed
Type 3 SVL circuit based shifter gives a power saving of up to 37.7% compared to TSPC based shifter and
18.6% compared to PDB logic based shifter in 65nm. For 90nm, Type 3 SVL circuit based shifter gives a power
saving of up to 33.8% compared to TSPC based shifter and 18.96% compared to PDB based shifter.
Fig.8 Power Comparison between proposed barrel shifter and conventional dynamic logic based shifter
The power consumption versus maximum clock frequency of 8 bit barrel shifter incorporating a type 3 SVL
circuit with m of 4 and barrel shifter without SVL circuit is summarized in Table 2. It is observed that proposed
shifter using type 3 SVL circuit gives better performance than other shifter designs.
Table 2. Power comparison for different 8 bit shifter as a function of frequency
Frequency(MHz)
100
200
300
400
500
Power(10-5 Watt) (at 90nm)
TSPC logic
PDB
Proposed
based shifter
based
Shifter
shifter
1.78
1.34
1.00
1.80
1.59
1.30
2.93
2.20
1.61
3.29
2.48
1.75
4.04
2.95
1.87
The results for the above table are plotted in Fig.9. Power consumption is a linear function of frequency. As can
be seen from the graph below, with increasing frequency, TSPC dynamic logic based shifter shows higher
power consumption than other shifter designs. But at higher clock frequency Type 3 SVL logic based shifter
gives lower power consumption.
Fig. 9 Power Comparison between proposed barrel shifter and conventional dynamic logic based shifter as a
function of frequency.
5.2
Power Analysis for ALU
Both the reduction in DIBL effect due to decrease in V dsn and increase in back gate bias (BGB) effect due to
increase in Vsub,n lead to further increase in Vthn. The increase in threshold voltage lowers the sub-threshold
leakage current and thus leakage power is reduced. Thus in this case, 8 bit ALU with SVL logic based shifter
shows lower power consumption than ALU with other barrel shifters. The power consumed by 8 bit ALU is
summarized in Table 3 and the plot is shown in Fig.10.
Table 3. Power comparison of 8 bit ALU with different barrel shifter
Power(10-5 Watt)
Vdd(volts)
ALU using
TSPC shifter
1v(90nm)
0.7v(65nm)
7.24
3.52
ALU using PDB
shifter
5.77
2.67
ALU using
Proposed
Shifter
4.83
2.37
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Fig.10 shows power plot of 8 bit ALU using different barrel shifter circuits. Proposed Type 3 SVL shifter based
ALU gives a power saving of up to 35.1% compared to TSPC shifter based ALU and power saving of up to
16.29% compared to PDB shifter based ALU in 90nm. For 65nm, Type 3 SVL shifter based ALU gives power
saving of up to 35.06% compared to TSPC shifter based ALU and 11.23% compared to PDB shifter based ALU.
Fig.10 Power comparison of ALU with different barrel shifter
CONCLUSION
An 8 bit barrel shifter incorporating SVL circuit was designed and simulated at 90nm and 65nm CMOS
technology. The power consumption of proposed shifter circuit shows advantage as compared to other dynamic
logic circuits. The total power consumption was significantly reduced with minimal overhead in terms of speed
and area. An SVL circuit can dynamically reduce drain-source voltages and increase substrate bias of OFF
MOSFETS in standby periods. This work explores and analyzes shifters and utilizes them in the design and
implementation of an ALU. In this work a high performance 8 bit ALU design was presented to minimize total
power consumption. The impact of SVL circuit technique on the shifter unit of arithmetic logic unit was
analyzed and was found to give lower power consumption for the ALU. Our simulation results indicate that, for
the 90nm and 65nm CMOS technologies it is possible to reduce the ALU total energy by approximately 33%
compared to ALU using TSPC shifter and 16%, as compared to ALU using PDB shifter with minimal delay
degradation.
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