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Test, Assembly &
Packaging TIMES
TM
“The IC Packaging & Test Authority”
© Copyright TAP TIMES 2011. Reprinted with permission.
Volume 2, Number 2
March 2011
Published 10X/Year
taptimes.com
SPECIAL TUTORIAL SERIES: FABRICATING OVERMOLDED QFN PACKAGES
Richard Otte
& Chris Pugh
cpugh@promex-ind.com
otte@promex-ind.com
Promex Industries
Santa Clara, Calif.
promex-ind.com
Otte
Pugh
The QFN Article Series
This is the first in a series of articles addressing
issues related to designing, fabricating and utilizing QFNs.
T
This installment concentrates on the basic overmolded QFN. Later articles will address customizing QFNs; their electrical parasitics;
open-cavity QFNs and QFNs built on substrates
to implement system-in-package modules.
he versatile plastic overmolded
QFN (Quad Flat, No-Lead) is the
package of choice for many semiconductor devices with 100 IOs or
.
less.
We view the QFN as a “packaging platform” enabling cost-effective modification to suit the specific
needs of the customer’s application and target markets.
The JEDEC standard copper leadframe-based
QFN provides a baseline platform suitable for the
majority of IC packaging applications.
The market is evolving, however, with an increasing need to address higher frequencies, electrical parasitics, RF performance, MEMS packaging,
stacked and multiple die configurations and the
related material synergies required to ensure optimal package performance.
JEDEC standard QFNs or DFNs (Dual Flat, NoLeads with leads on only two sides rather than all
four) are available in square metric sizes ranging
from 2 x 2mm to 12 x12mm in leadcounts from 4 to
100 with an overall thickness of 1mm and lead pitch
of 0.65mm, 0.5mm and sometimes 0.4 mm available.
Figure 1 shows a variety of these standard
QFNs. The table at right lists 32 sizes of QFNs and
DFNs that are available off-the-shelf.
Fabricating Leadframe-Based QFNs
Figure 2 shows the process flow to package
semiconductor chips in QFNs using a leadframe and saw singulation.
An alternate singulation process is used for high
volumes. That singulation process utilizes a mold
with individual pockets for each QFN and a matching punch set to singulate the devices.
The tooling cost of ~$100,000 per size is justifiable for very high volumes. (The sawing process
illustrated here, however, is the most common.)
1. QFNs range in size from 2mm x 2mm to 12mm x 12mm
with 6 to 100 leads.
Test, Assembly
& Packaging
TIMES
Test,
Assembly &
Packaging January-February
TIMES
March2011
2011
OVERMOLDED PACKAGES
Page 1
Off-the-Shelf DFN and QFN Sizes Available
QFN
DFN
Dimension
2 x 2mm
2 x 3mm
3 x 3mm
3 x 3mm
3 x 3mm
4 x 3mm
4 x 4mm
4 x 4mm
5 x 5mm
5 x 5mm
5 x 5mm
6 x 6mm
6 x 6mm
7 x 7mm
7 x 7mm
8 x 8mm
8 x 8mm
9 x 9mm
10 x 10mm
10 x 12mm
Lead Count
8
12, 16
20
16
20, 24
20
28, 32
36, 40
40
48
48
56, 60
52, 56
68
64
72
100
Lead Count
6, 8, 10
10, 12
8, 10
12
12
Lead Pitch in.
0.5
0.5
0.65
0.5
0.4
0.5
0.65
0.5
0.65
0.5
0.4
0.5
0.4
0.5
0.4
0.5
0.4
0.5
0.5
0.4
2. The Saw-Singulated QFN Fabrication Process
pad so that after molding, as explained later, the
metal elements are “gripped” or “captured” more
effectively by the molding compound.
The major process flow steps for a plastic
overmolded, saw-singulated QFN are:
• Die attach to lead frame array
• Wire bond die to lead frame sites
• Over-mold the lead frame arrays
• Ink stamp or laser mark individual
devices
• Saw-singulate individual packages
• Test & bin
• Pack for shipment
Packaging Die in QFNs
The packaging process starts with a leadframe, as shown in Figure 3. The leadframe
has four arrays of QFN sites, is fabricated
from a copper alloy and is usually 200 microns (~0.008”) thick.
The leadframe is etched from both sides using
etch patterns that are slightly different.
The etch pattern from the side that will eventually be mounted on the circuit board has more
metal removed from the edges of leads and the die
3. This is a typical QFN leadfame with four arrays. The overall dimensions are ~ 75mm x 200mm.
After etching, the leadframes are patternplated. A standard plating metallurgy uses nickel,
paladium and gold.
A nickel-plated layer uses a thickness of 0.5 to
2.0 microns; when palladium is employed, the
thickness ranges from 0.02 to 0.15 microns; gold is
plated from 0.003 to 0.015 microns.
A Universal Plating System
This plating system has the advantage that
it is “universal”—meaning it wire bonds
well, solders well and has a reasonable shelf
life.
The amount of gold is low enough to avoid the
embrittlement of solder joints that occurs with
higher amounts of gold.
Test, Assembly & Packaging TIMES
OVERMOLDED PACKAGES
Plating is required only on those surfaces where
wire bonding or solder will occur; ideally all other
surfaces will be bare copper to which molding compound and die attach adhesives adhere better than
they do to gold-plated surfaces.
Ideally, all of the bare copper surfaces will be
treated to improve adhesion. Figure 4 shows the
opposite side of the leadframe in Figure 3.
4 Opposite side of the leadframe of Figure 3 shows the layer
of tape used to protect the surfaces from mold compound
bleed.
This side has a layer of tape that covers the
plated surface to protect it during the molding
process that will be performed later.
Preventing ‘Flash’
A common problem during molding is getting “bleed” or “flash” from the mold compound onto metal surfaces. The tape
protects these surfaces from bleed.
Die Preparation
The standard height of QFNs is 1mm. To
achieve that thickness, the die—while still
on wafers—must be backgrinded to a thickness of 250- to 300 microns.
After backgrinding, wafers are sawn to singulate
the die. Sawn die go into the die attach process either “as sawn” on “bluetape,” a common industry
standard sawing aid, or are first “plated” into/onto
waffle packs or GelPaks.
Die may or may not be tested while still in the
wafer state before backgrinding. If tested, known
bad die are rejected either when plated to waffle
packs or GelPaks, or when the die are removed
from blue tape during the die attach process.
March 2011
If die have not been tested at the wafer level,
they are tested and “binned” after packaging, as
shown in Figure 2.
Die Attach
The QFN assembly process begins with dispensing the die attach adhesive and placement of the die.
This is a critical process for QFNs. The die attach material must form a joint under the die with
a minimal amount of voids and must extend beyond the edges of the die to form a “nice” fillet.
Too much die attach material will result in the
material flowing onto the wire bond sites causing
multiple problems.
Too little, however, will result in excess voids
under the die that may result in cracking of the
die during wire bond or in a poor thermal path,
resulting in excess temperature rise in the die during
operation.
Wire Bonding
After the die attach material is cured, the arrays go to wire bonding. QFN wire bonding
is typically done with 0.001” gold wire using
thermosonic ball bonding.
Bonding to the die is usually straightforward.
Bonding to the
leadframe fingers,
however, can be
challenging.
The difficulty
arises from the fingers in the leadframe resting on
the tape shown in
Figure 4 and from 5. This photo shows the die attach matethe fingers not rial formiing a fille around the entire die.
being held tightly. A close-up of several adjacent
sites of a typical devices is shown in Figure 5.
Careful setup and tooling of the wire bond
process is necessary to achieve high quality bonding. Process control is very important at this stage.
A dummy die (not a “real” die) is shown, which
is used for test and development purposes. During
singulation, the saw will remove the backbone to
isolate the individual leads.
Test, Assembly & Packaging TIMES
OVERMOLDED PACKAGES
Overmolding of the Die Arrays
After all the die are wire bonded, the leadframe is placed in a mold with which it is
compatible.
Molding transfers molding compound from a
“pot” into the cavity where the compound flows
around the wire bonds, the chip and into all of the
small spaces etched into the leadframe.
Marking and Singulation
After molding, the arrays of parts are ready
for marking. Both laser marking and pad
printing are commonly used to mark overmolded devices, including QFNs.
After marking, the parts are sawn into individual units and are ready for testing and binning.
The Finished QFN
Figure 6 is a cross section of a finished QFN
illustrating the features and results of the
process.
The most common overall QFN height is 1.0
mm. Heights from 0.4 mm to 1.4 mm are available,
however, if the die and wire bonding are compatible with the low profile or if more height is needed
to accommodate stacked die.
Conclusion and Summary
The QFN has emerged into the mainstream
during the last five years and is now the
package of choice for chips with 100 leads
or less.
This package offers many benefits: They include low cost due to minimal material content and
ease of manufacturing; good heat-sinking through
the large die pad; low parasitics through the short
leads; small size; ease of assembly using conventional pick-and-place equipment; low tooling cost
(< $10,000); and short (~ five week) lead time to
tool a custom configuration.
A Very Versatile Package
The versatility of the QFN is another benefit, and the package allows a single die,
March 2011
stacked die or SiPs built on a substrate—
rather than a leadframe—to be packaged.
The standard leadframe-based QFN is morphing in several directions, all of which retain these
benefits.
6. A typical QFN cross-section shows the die attach material forming a fillet around the entire die.
Further Reading
1. The Promex web site offers details of JEDEC
standard, off-the-shelf QFNs. Visit www.promexind.com.
2. See IPC Standard 7093 Design and Assembly Process Implementation for Bottom Termination SMT Components.
This standard is in final draft form and will be
issued shortly. It contains much information on
standard, overmolded QFNs and related “bottom
terminated” components.
The QFN has emerged into the
mainstream during the last five years
and is now the package of choice
for chips with 100 leads or less.
Mr. Otte has been president and CEO of
Promex Industries since 1995. Earlier, he served
for more than 22 years in various posts with Raychem. He earned both a BSEE and an MSEE from
MIT.
Mr. Pugh is Promex’ vice president for sales and
marketing. He earned a bachelor’s degree from
Simon Fraser University, Vancouver, B.C., Canada,
and an MBA from the University of San Francisco.
C
Test, Assembly & Packaging TIMES
April 2011
SPECIAL TUTORIAL SERIES: FABRICATING OVERMOLDED QFN PACKAGES
Richard Otte
& Chris Pugh
cpugh@promex-ind.com
otte@promex-ind.com
Promex Industries
Santa Clara, Calif.
promex-ind.com
Otte
Pugh
Custom QFNs Fill A Growing Need The
T
Part 2 in the Series
This is the second in a series of articles addressing issues
related to designing, fabricating and utilizing QFNs packages.
This installment concentrates on the need for customizing plastic over molded QFN’s. The first article appeared in the March issue.
he first in this series presented the
QFN as a flexible and cost-effective “packaging platform” ad- aptable to the evolving needs of the
customer’s application and target
markets.
In today’s environment, there is an increasing
need to address higher frequencies, RF performance, MEMS packaging and stacked/multiple die
configurations that need packaging solutions that
have evolved beyond the original JEDEC standard
QFN outline.
Custom QFN’s Made Simple
The JEDEC standard size, height and footprint may not always result in package characteristics suitably optimized for high
frequency, MEMS packaging or multiple
and stacked die applications.
The versatility of the QFN package leadframe
array concept allows cost effective customization in
a relatively short time period to address a specific
package dimension or performance objective.
Non-JEDEC standard features are usually accommodated without difficulty with a custom leadframe design.
1. Typical QFN leadframe is comprised of four zones.
The overall dimensions are ~ 75 mm x 200 mm.
Some typical QFN package variables that could be
customized include:
1.
Height: thinner or thicker than the 0.9 mm
+/- 0.1 mm nominal JEDEC standard. Overall
stand-off heights of less than 0.4mm have been
achieved.
2.
Leads: varying the number on each side, the
lead length and lead width, custom lead pitches,
custom distance between the die attach pad and
the lead itself. Tying various leads directly to the
die attach pad. Non symmetrical lead counts and
different sized leads within the same package are
also attainable. Short leads provide low parasitics.
3.
Die attach pad (DAP): made larger to increase thermal efficiency or smaller to fit small die
sizes better. Custom shapes or multiple DAPs are
also possible.
4.
Board level footprint: as a“drop-in” replacement for an existing board level component or customized for a specific requirement.
5.
Package shape: rectangular rather than
square.
6.
Leadframe finish: custom plating options
(for example, spot silver) to accommodate down
bonds to the die attach pad better; lead frames optimized for copper wire bonding.
7.
Package evolution: flip chip used as a replacement for traditional wire bonding.
Custom Leadframes Are Cost-Effective
The fabrication process for leadframebased QFNs lends itself to customization as
long as basic design rules are followed.
Test, Assembly & Packaging TIMES
One major advantage of the leadframe-based
QFN is the use of leadframes with standard outside
dimensions that fit a standard mold tool.
Saving Mold Tooling Cost
QFN “sites” of any size can populate the
standard leadframe array. This approach
eliminates the need for a brand new, dedicated mold tool each time a new QFN package is required.
Only the leadframe requires a redesign to the
desired new QFN configuration, significantly reducing NRE tooling expense.
NRE for a new leadframe is typically in the
$5,000 range with a standard lead time of four to
five weeks.
While most leadframe arrays are populated
with only one size of QFN, it is not impossible to
mix two or more sizes within separate zones of the
lead frame/mold combination.
The leadframe array shown in Figure 1 has four
separate zones all incorporating the same QFN.
Reducing NRE Costs
While it is wise—often essential—to keep all
of the sites within each of the four zones the
same, each of the four arrays could be of a
different configuration, significantly reducing NRE tooling costs for multiple, unique
configurations.
Figure 2 shows a custom leadframe with several
interesting features: First, the QFN is not square,
but rectangular, ~ 5mm x 4mm.
Obviously, any reasonable rectangular dimensions are viable.
Leads Are Tied to Die Attach Pad
The second feature of this custom site is
that, for desired electrical reasons, many of
the leads are tied directly to the die attach
pad (DAP), providing a solid electrical
ground.
Again, virtually any combination of isolated and
“grounded” leads is viable in a custom leadframe.
A third option, not illustrated in this example,
is to segment the die attach pad. That is viable as
April 2011
long as the leadframe “hangs together.” Special design rules apply to QFNs with segmented DAPs.
QFNs are Morphing in
Several Directions
The ability to quickly
and inexpensively customize QFN’s has resulted in several application “forks” from
the original, singledie JEDEC standard
2. A custom leadframe illuspackage.
Today, this versatile trates rectangular a QFN with
package platform com- leads tied to the die pad.
monly incorporates stacked die, multiple die, passives, custom lead frame finishes, round and RF
ribbon wire bonding including combinations of the
two, as well as die-to-die wire bonding and flip
chip.
Figure 3 shows a cross section of a typical custom stacked die application.
3. QFN customized for stacked die
As a reminder, the most common overall QFN
height is 1.0mm, but overall heights from 0.4mm
to 1.4mm are achievable if the die stack and accompanying wire bond loop heights are carefully
controlled to provide an adequate mold cap.
The most common overall
QFN height is 1.0 mm, but overall
heights from 0.4 mm to 1.4 mm
are achievable . . .
Test, Assembly & Packaging TIMES
Custom Board-Level Footprints
Two examples of non-JEDEC standard
footprints are illustrated in Figures 4a and
4b, which show both die attach pad segmentation and customized lead size and
features.
Conclusion and Summary
Customization of QFN’s addressing specific market needs or applications may be
considered generally routine and cost effective.
Custom QFNs should not be considered barriers to anyone who concludes a JEDEC standard
QFN will not suit their purposes.
Further Reading
April 2011
The Promex web site offers details of
JEDEC standard off-the-shelf QFNs and
additional sources. Visit www. promexind.com.
4. Examples of non-JEDEC-standard footprints
Mr. Otte is president and CEO of Promex Industries. Mr. Pugh is vice president of sales and
marketing.
Test, Assembly & Packaging TIMES
May 2011
SPECIAL TUTORIAL SERIES: FABRICATING OVERMOLDED QFN PACKAGES
Electrical Parasitics in QFNs
Richard Otte
& Chris Pugh
cpugh@promex-ind.com
otte@promex-ind.com
Promex Industries
Santa Clara, Calif.
promex-ind.com
W
Otte
Pugh
Part 3 of 4
This is the third in a series of articles addressing issues
related to designing, fabricating and utilizing QFN packages. The first article appeared in the March issue.
e conducted a study to determine electrical parasitics at
GHz frequencies of JEDEC
standard, leadframe-based,
saw-singulated, plastic overmolded QFNs by first extracting the S parameters and then calculating the electrical
parasitics.
We learned overmolded QFNs in sizes from 3 x
3mm to 7 x 7mm will function well at frequencies
as high as 20GHz.
(Table 1 below presents a simple summary of
the results. More detailed values and the methodology by which the values were measured are described below.)
Min.
Max.
C11 pF
L11 nH
C12 pF
L21nH
0.262
1.442
0.086
0.598
0.212
0.825
0.004
0.228
Table 1. Min & Max Parasitics Measured in Overmolded QFN
Sizes Between 3 x 3 & 7 x 7mm
Configuration & Fabrication of Test Sample QFNs
Two types of die were procured; one had isolated wire bond pads; the second bussed all of
the bond pads together.
Three sizes of each die type were obtained (1 x
1mm with 16 bond sites; 2.5 x 2.5mm with 32 bond
sites; and 4 x 4mm with 48 bond sites.)
Six standard QFN leadframe sizes were chosen
(shown in the table on the next page):
Test, Assembly & Packaging TIMES
Electrical Parasitics in QFNs
Size, mm x mm
Leadcount
Lead Pitch, mm
5x5
32
0.5
3x3
7x7
5x5
5x5
7x7
16
48
0.5
0.5
20
0.65
56
0.4
40
May 2011
0.4
Table 2. QFNs fabricated and measured each using two types of
custom test die
This resulted in each of the six sizes having two
types of connections; in one type, all of the leads were
“open” because they interfaced to the die with pads.
In the second type, all of the leads were shorted because they were bonded to the fully metalized die.
Standard Assembly Processing
All test die were attached to the appropriate
leadframe and ball bonded with 0.001” gold
wire with a bond from either the open metal
pad on the die or the shorted metal pad on the
die to each QFN finger.
The die size and wire bonding programs were
identical for the two types of die in each of the six sizes
of QFNs. That’s important because the parasitics vary
somewhat with die size and wire bond configuration.
Measurement Method to Extract QFN Parasitics
The conventional microprobe method of
measuring high frequency (>1 GHz) parameters was not utilized.
A circuit board (shown in the photo) was fabricated with six probe sites.
Coax cables, SMA connectors and 50-Ohm microstrip traces on the PWB were used to interface between the network analyzer and the circuit card.
We learned overmolded QFNs in sizes from
3 x 3mm to 7 x 7mm will function well
at frequencies as high as 20GHz.
Photo shows one of six sites on the circuit card.
The site above is used to connect to 0.5mm
pitch side-by-side contacts on a QFN of any size.
Two similar sites are available to contact to 0.4mm
and 0.65mm pitch QFNs.
Three additional sites are available to contact
corner pads that are at 90o to each other.
The die size and wire bonding
programs were identical for
the two types of die in each
of the six sizes of QFNs.
Focus on 5 x 5mm
The measurement effort focused on the 5
x 5mm / 32-lead package with 0.5 lead pitch.
The 3 x 3mm and 7 x 7mm/0.5 pitch packages
were measured to show the variation with size; 5 x
5 packages with 0.4mm- and 0.65mm-pitch were
also measured to demonstrate the impact of pitch
on the parasitics.
The parasitics were measured at two points on
the QFNs: (a) center pairs of IOs and (b) corner
pairs of IOs.
Measuring the Data Points
In general, five measurements were made
for each data point. The resulting standard
deviation was 5 percent or less of the average value of all of the parameters.
The actual measurements, data analysis and extraction of the parasitics (C11, C12, L11, L12, Zo,
etc.) were made by a third party, Dr. Eric Bogatin of
Bogatin Enterprises Inc., a leading industry signal
integrity expert.
Test, Assembly & Packaging TIMES
Electrical Parasitics in QFNs
The steps in making a set of measurements
are:
1. Measure S11 for the test card without a
QFN and the contact points open.
2. Measure S11 for the test card without a
QFN and the contact points shorted together.
3. Measure S11 with the QFN with the open
lead die contacting the test card contact
points.
4. Measure S11 with the QFN with the
shorted lead die contacting the test card
contact points.
S11 was measured and plotted over a broad frequency range ~ 10 MHz to 8GHz resulting in an accurate measure of S11 for the above four cases.
S11 for the open lead QFN results over the frequency range measured by taking the difference between S11 as measured with the “opens die” QFN
and the open contact point test card (measurements 1 and 3 above).
Likewise, by taking the difference between S11
for the shorted die QFN and shorted contact test
card (measurements 2 and 4 above) S11 for the
shorted lead QFN results.
Since S11 is related to Zo, the value of C11 can be
computed using the “opens” value of S11 vs frequency with the equations:
Zo = 50 x ((1+S11)/(1-S11))
and
C11 = 1/jwZo
Likewise, L11 can be computed using the
“shorts” value of S11 versus frequency with the
equation
L11=jwZo
The values of C21 and L21 can be computed in a
similar manner. Strictly speaking, the extraction is
accurate for only that particular die size and wire
bond pattern.
May 2011
The S parameters and Zo presented are complex
numbers and an in-depth explanation is beyond the
scope of this article.
Readers are encouraged to view the further
reading section for appropriate links and to visit
www.promex-ind.com
Conclusion
The computed values of C11, L11, C21 and
L21 may be used in a simple lumped parameter model to characterize the QFN packages as long as the dimensions, meaning
mostly wire bond length, are less than 1/10th
of the wavelength of the frequency of interest.
Since these lengths are < 1 mm, the lumped parameter model should be good for signals with a
wavelength of 10mm or more.
A 10mm wavelength in this molding compound
(dielectric constant of 4) corresponds to a frequency of 15GHz.
Realistically, the QFN, especially the small
sizes, will have a minimal impact on signals of
much higher frequencies. Further work is required
to determine the exact limits.
Further Reading
The Promex and Bogatin Enterprises web sites
offer details of this QFN parastics study. Visit
promex-ind.com or bethesignal.com.
Mr. Otte is president and CEO of Promex.
Mr. Pugh is vice president for sales and
marketing.
Test, Assembly & Packaging TIMES
June 2011
SPECIAL TUTORIAL SERIES: FABRICATING OVERMOLDED QFN PACKAGES
Richard Otte
& Chris Pugh
cpugh@promex-ind.com
otte@promex-ind.com
Promex Industries
Santa Clara, Calif.
promex-ind.com
Otte
Pugh
Substrate-Based QFNs
Innovate the System-in-Package
T
Part 4 of 4
This is the final installment in a series of articles addressing issues related to designing, fabricating and utilizing
QFN packages. The first article appeared in the March
issue.
he plastic overmolded QFN (Quad
Flat No-Lead) has evolved into the
package of choice for many semiconductor devices with 100 IOs or
less.
QFNs may be viewed as a “packaging platform”
enabling cost-effective modification to suit the specific needs of the customer’s application and target
market.
A copper leadframe-based JEDEC standard
QFN provides a baseline platform highly suitable
for most IC packaging applications that use a single
die.
A Versatile Packaging Platform
The versatility of the QFN packaging concept allows consideration for addressing
evolving market applications where a substrate, rather than a lead frame, is a better
alternative.
System-in-Package parts developed using the
QFN platform approach enable a miniaturized, reliable and cost-effective chip-scale package while
providing excellent manufacturing yields.
Common substrate materials utilized are FR-4
and FR-5 as well as PTFE and BT material for highfrequency RF applications.
The Land Grid Array
The footprint of a substrate-based QFN is
sometimes referred to as a Land Grid Array
(LGA).
Surface-mount side (backside) solder pad configurations may duplicate those of a typical QFN
using locations around the package periphery, or
alternately, a more complex LGA base substrate
may be designed with custom solder pad layouts.
LGAs often incorporate HDI (high density interconnect) features such as buried and blind vias
or application-specific thermal management features.
1. Surface mount side of ~75 mm x ~200 mm custom substrate with four arrays of 16 SiP sites.
Substrate Based QFNs
The two substrate images shown in Figures
1 and 2 are the opposing sides of a custom
FR-4 substrate array designed as a platform
for a SiP using a QFN-like configuration.
The SMT attach points for an LGA are simply a
layer of metal on a circuit board.
Since these substrates are usually designed with
four metal layers, the SMT footprint can have almost any configuration.
The footprint shown in Figure 1 has a single row
of contacts around the periphery but differs from a
conventional QFN footprint because the typical die
attach pad of a JEDEC standard leadframe-based
package has been replaced by two separate pads.
2. Component side of the custom SiP substrate shown in Figure 1 prior to overmolding. X-outs are defective sites.s.
Test, Assembly & Packaging TIMES
June 2011
FABRICATING QFNS
These are likely to be ground and power for
what is most commonly a low-power SiP.
Even though this substrate has four metal layers, its overall thickness is still approximately 200
microns and is similar to the conventional leadframe-based QFN leadframe.
Importantly, these substrates can usually be
over-molded using the same tooling used for the
leadframe-based QFNs, thus saving on tooling
costs.
Enhanced Flexibility
An important benefit of using a substrate is
the enhanced interconnect flexibility enabled by the circuit board-like substrate.
While the example shows peripheral SMT
pads, almost any pattern is viable, such as multiple
rows or a completely filled-in array.
Circuit board substrates may be fabricated in
less lead time and with less cost than a new or custom leadframe.
Any substrate layout revisions or future design
changes are more efficiently and relatively inexpensively managed with the LGA substrate approach.
System parts placed on the component side are
cost-effectively interconnected as desired using
conventional automated pick-and-place SMT and
direct chip attach methods.
Saw singulation is an easier process as the
“softer” materials used in an LGA-based QFN SiP
eliminate the need for sawing through a hard copper leadframe.
Typical SiP Process Flow
Figure 3 shows the process flow to build an
LGA substrate-based SiP in a QFN-like package.
The first step is usually conventional SMT assembly. The requirement to perform flip chip or
wire bonding assembly steps after the SMT process
requires care in the SMT process to avoid contaminating the contact points for the flip-chip attach
and wire bond sites.
Modern SMT commonly allows counts of 30+
parts in a 10mm x 10mm x 1 mm final size package.
3. SIP Process Flow
Typical SiPs include multiple die, either in chipscale packages, wire bonded, or flip-chip attached,
and conventional 0402, 0201 and 01005 SMT-size
parts.
After component placement, the substrate array
is over-molded.
Overmolding Needs Tight Process Control
This overmolding process for complex SiPs
requires tight process control to avoid wire
bond sweep; avoid excess force that would
move or shear components attached to the
substrate; and completely fill the mold cavity to eliminate voids caused by component
size, positioning and layout interfering with
mold compound flow.
After marking, the parts are sawn into individual units and are ready for testing and binning.
Apparently evolving from the leadframe-based
QFN JEDEC standard, the most common overall
QFN/SiP/LGA height is 1.0mm.
Heights from 0.4 mm to 1.4 mm are available,
however, if the die and wire bonding are compatible with the low profile or if more height is needed
to accommodate higher components.
Tape & Reel
Like standard QFNs, SiP/LGA versions may
be placed on tape and reel, thereby turning the
complex SiP package into a “standard” SMT component for the next level of board assembly.
Test, Assembly & Packaging TIMES
FABRICATING QFNS
Substrate-based SiPs for RF Applications
QFN-like SiPs for the RF market may be addressed by the use of PTFE or BT laminates
as the substrate base.
Both materials offer excellent dielectric properties at high frequencies, as well as advantages in
flexural strength, modulus, thermal expansion
characteristics and glass transition temperatures
over conventional FR-4.
These substrates also exhibit fine processing
characteristics for automated SMT, various types
of wire bonding or plastic over-molding.
RF paths need to be carefully designed to minimize wire bond length and overall loop height.
Above 20 GHz, generally RF ribbon or RF wedge
bonding replaces gold ball bonding with round
wire.
Reaching Its Performance Peak
At these higher frequencies, plastic overmolding also begins to reach its performance peak.
The solution is a QFN substrate-based package
that is assembled with a separately attached
“domed” plastic lid, eliminating the over molding
process step.
The B-stage epoxy coated lid exactly fits the
package outline and is applied to the substrate as a
final step in the assembly process. The result is an
air cavity substrate-based QFN SiP suitable for RF
applications.
Conclusion & Summary
The JEDEC standard leadframe-based QFN
is a versatile package for many market applications with 100 leads or less.
Viewing the QFN as a “packaging platform” allows the designer to innovate market need applications relatively inexpensively and with dramatically
shortened lead times using stable assembly
processes.
QFN packages based on LGA substrates offer
significant advantages for use as a similar base platform addressing the growing system-in-package
market.
June 2011
Applying a domed lid to a PTFE material or BT
laminate substrate-based QFN provides a high-performance air cavity SiP suitable for the rapidly
growing RF market.
The Promex web site offers details of opentooled QFNs as well as all articles in this series. (Visit www.promex-ind.com.)
2. See “IPC Standard-7093 Design and Assembly
Process Implementation for Bottom Termination
SMT Components”. It contains much information
on standard overmolded QFNs and related “bottom
terminated” components.
Promex Industries Inc. is a service provider to
many semiconductor companies, as well as a participant in industry efforts including the writing of
IPC Standard 7093 referenced above. Mr. Otte is
president and Mr. Pugh is vice president-sales and
marketing.
QFN Packaging
!
RoHS compliant QFN/ TQFN/ DFN assembly. Stacked die,
MEMS packaging & SiP’s (2D, 3D & SMT). ITAR registered,
ISO 13485:2003 Medical certified.
Silicon Valley’s Packaging Foundry
www.promex-ind.com
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