a 10 Gbps Burst-Mode Clock and Data Recovery Circuit with Continuous Clock Output Runxiang Yu, Roberto Proietti, Shuang Yin, and S.J. B Yoo Junya Kurumida National Institute of Advanced Industrial Science and Technology Ibaraki, Japan [email protected] Department of Electrical and Computer Engineering University of California at Davis, Davis, USA [email protected] Abstract—This paper presents a 10-Gbps burst-mode clock and data recovery (BM-CDR) circuit based on the phase picking method. Experiment demonstrates the proposed BM-CDR circuit is able to align the burst-mode incoming data to the local clock with a maximum phase misalignment of ±π/8 within 20 ns. Keywords-Burst mode; clock synchronization; multiphase clock I. and data recovery; bit extracted data clock with four phase-delayed copies of the local clock at the same rate as the data. Two important characteristics of the BM-CDR are its phase acquisition time and accuracy of the phase alignment. Here, a phase synchronization time of 20 ns and phase alignment accuracy of ±π/8 are achieved which are sufficient for 10 gigabit Ethernet PON (10G-EPON) application according to IEEE802.3 av 10G-EPON standards and may be also useful for future optical packet switching network. INTRODUCTION The rapid growing of the last mile solution such as passive optical networks (PONs) activates research on burst mode data operation where the optical line terminal (OLT) must deal with asynchronous packets with different amplitude and phase, necessitating clock and data recovery (CDR) circuit with fast clock recovery and data retiming. In future optical packet switching (OPS) network, burst mode operation is essential to conduct burst packet aggregation at the OPS edge router . In both cases, a burst-mode receiver (BMRx) plays a key role which is responsible for amplitude and phase recovery at the beginning of every packet. A generic schematic of a BMRx is shown in Fig. 1. At the front end of the BMRx is a BM limiting amplifier (BM-LA) with automatic gain control (AGC) and automatic threshold control (ATC) which is responsible for amplitude recovery. Fast clock and data recovery (CDR) together with phase acquisition is then performed by a BMCDR. This paper focuses on the BM-CDR aspect of the BMRx. Among the existing solutions,  incorporates gated voltage controlled oscillators (GVCO) to acquire rapid phase locking but results in higher phase noise as it does not filter out the input jitter. More seriously, the gating behavior would cause momentary fluctuation on the recovered clock, potentially incurring undesired jitter and inter-symbol interference (ISI). BM-CDR based on injection locking technique suffers from issues such as limited locking range, process, temperature and supply (PVT) variation and weak injection signals . Oversampling in time requires a clock frequency higher than the bit rate while oversample in space only using multiphase clock with a frequency equal to the bit rate . Also it is desirable for a BM-CDR circuit to align the burst data to a local clock so it provides a continuous clock output for existing PON Large scale integration (LSI) and RocketIO transceiver on field programmable gate array (FPGA) for data processing. Here the proposed BM-CDR technique is based on phase picking method by mixing the This work was supported in part by DoD contract #H88230-08-C-0202 Electrical path BMRx BM-LA PD/TIA AGC This work BM-CDR ATC Figure 1. Generic schematic of a burst mode receiver. PD: photo-detector; TIA: transimpedance ampfilier; BM-LA: burst mode limiting amplifier; AGC:automatic gain control; ATC:automatic threshold control. II. Proposed 10GHz BMCDR Circuit AMP 1:4 AMP Fanout AMP Buffer AMP LO O/E CIRCUIT DESCRIPTION AND IMPLEMENTATION 1:2 Fanout Buffer Clock Extraction NRZ BPF LA to RZ Delay Line 1:4 Fanout Buffer 0º 90º 180º Comparator Comparator Comparator 270º Comparator 1:4 Fanout Buffer 0º 90º 180º FPGA 4:1 selector 270º Figure 2. Schamtic of the proposed 10Gbps BM-CDR. O/E: optical to electrical converter; LA: limiting amplifier; AMP: amplifier; BPF:bandpass filer The proposed BM-CDR is implemented for operation at 10 Gbps for non-return-to-zero (NRZ) data. The main building blocks include an Atlys Spartan-3 FPGA development board from Digilent and a custom designed printed circuit board (PCB) with individual chips from Hittite Microwave built in as shown in Fig. 2. All the major components are listed in Table. I. The incoming optical data is O/E converted then buffered. Four time-delayed and phase-delayed copies are prepared for latency. Here four comparators with 700-ps propagation delay are employed which are equivalent to a 2-bit ADC. The phase alignment accuracy of this configuration can be expressed as s = ±π / 2n (1) when n is the number of mixers employed in this case. 1:4 Fanout Output (V) the 4:1 selector. After NRZ-to-RZ conversion, data clock is extracted by a high Q band-pass filter (BPF) with a Q of 200. While it is possible to insert the system clock as a subcarrier inside the transmitted signal , it complicats the hardware required for the transmitter. The extracted clock is then amplified and phase delayed before entering the RF mixers to frequency mix with the four copies of the local clock for phase detection. The threshold of the four comparators is set to 48 mV which is chosen according to the maximum mixer output voltage in the worst case as described in Fig. 3 and Fig. 5. By matching the mixer outputs to a look-up table, the FPGA selects one of the four parallel burst mode packets at the selector inputs which has the largest phase margin as the optimum recovered data and feed them to the next stage (either a PON LSI or RocketIO Transceiver on a FPGA) for further data processing. A D flip-flop (DFF) could be easily added at the BM-CDR output for data retiming. 0 Port 1 Port 2 -0.2 Port 3 -0.4 Port 4 -0.6 150 100 Time (ps) 50 0 200 Figure 4. Measured phase delayed copies of the Data before the 1:4 selector TABLE I. Model Number LIST OF COMPONENTS Description Function Vendor name HMC720LC3C 14Gbps 1:2 Fanout fuffer Hittite HMC940LC4B 13Gbps 1:4 Fanout fuffer Hittite HMC958LC4B 14Gbps 4:1 Selector Hittite HMC721LC3C 14Gbps XOR/XNOR gate Hittite HMC914LP4E 12.5Gbps Limiting amplifier Hittite HMC788LP2E DC-10 GHz Gain block Hittite Hittite National semiconductor TLD 7-10GHz double balanced mixer LMH7323 Quad 700ps high speed comparator Atlys Spartan-6 LX45 FPGA Board Digilent Bandpass filter 10GHz band-pass filter Q=200 RLC Electronics 0 -0.5 -180 -90 0 90 Phase delay (Degree) (b) Mixer output (a.u) Mixer output (a.u) 0.5 III. Signal 1545 nm HMC171C8 (a) The multiphase clock/data generation is achieved by the 1:4 fanout buffer with the electrical co-planer waveguide with ground plane (CPWG) on the PCB. The measured delay deviation from the target value is within ±2ps which is reasonable considering the skew value (±3ps) specified in the HMC940LC4B datasheet. Four phase delayed copies of the data are recorded as show in Fig. 4 EXPERIMENT AND DISCUSSION t t t 50:50 FDL IM EDFA RF driver O/E 10G BMCDR 50:50 TDL t PPG CLK 10GHz Figure 5. Example of a figure caption. (figure caption). IM: Intensity modulator; TLD: tunable laser didoe; PPG: pulsed pattern generator; FDL:fixed delay liner; TDL: tunable delay line; CLK: Clock; 50:50: 50:50 fiber coupler 0.5 0 -0.5 -135 -45 45 135 Phase delay (Degree) Figure 3. Mixer output as a function of phase delay (a) best case (b) worst case Theoretically the phase delay between the extracted clock and the local clock can be uniquely identified by frequency mixing of the extracted clock with two phase delayed copies of the local clock . But low speed (<1Gsps) analog-to-digital converters (ADC) which are needed later on to digitize the mixer outputs will inevitably introduce significant conversion latency. So there is a trade-off between cost, resolution and Setup in Fig. 5 is used to generate burst-mode data with varying phases. The pulse pattern generator (PPG) generates a periodic 1024-bit long sequence (constructed using 27-1 PRBS) followed by a 1546-bit long guard time. The electrical sequence is amplified and fed into a 10-Gbps optical intensity modulator (IM) to modulate the output of a tunable laser diode (TLD) at 1545 nm. The modulated optical signal is amplified and split into two by a 50:50 fiber coupler. After proper delay adjustment, the optical signals in the two branches are interleaved by another 50:50 fiber coupler. The guard time between the adjacent packets either 23.5 ns (235 bits '0') or 27.7 ns (277 bits '0'). In the end, the interleaved signal is O/E converted and sent to the proposed BM-CDR. The minimum time needed for synchronization under current configuration is approximately 20ns which is determined mainly by the mixer output rising time (~10ns when using a BPF with a Q of 200 as shown in Fig. 6), the FPGA decision time (<4ns, 2 clock cycles when clocking @500MHz) and the 4:1 selector select time (< 100ps). Figure 6. Rising/falling edges of the mixer outputs when using bandpass filter with a Q of 200 for clock extraction. Top: best case, Bottom: worst case Mixer output rising/falling time depends on the BPF used to extract the data clock. A BPF with smaller Q can be used to reduce the rising/falling time of the mixer output. The optimum Q for this particular application is still under investigation. The scope trace of the extracted clock and the reference clock is illustrated in Fig.7 showing no degradation in terms of jitter. Error free Operation is achieved using the configuration as shown in Fig. 5 under various phase delay between adjacent packets. This implies the delay of the clock path tracks that of the data path very well and a retiming DFF in the next stage will always sample in the vicinity of the data eye. The amplitude electrical input of the BM-CDR is kept above 100 mV which is specified as the minimum input voltage for the 1:2 fanout buffer (HMC720LC3C) in its datasheet. To measure BER as a function of input optical power requires additional BM-LA as shown in Fig. 1 which is not available at this time. The proposed BM-CDR technique assumes that the extracted clock and the local reference clock are matched in frequency since the same clock source is used for the 10Gbps RZ-OOK transmitter and the BM-CDR in the experiment. However, error will occur if the frequency walk-off between the two clocks is greater than 1/4 of the bit time cross the entire packet. The commercially available electrical 10-GHz local oscillators (from Microwave Dynamics) have a typical frequency stability of ±5 part-per-million (ppm). Therefore without any modification, the proposed BM-CDR circuit can accommodate packet length up to 25,000 bits without error. For longer packets, the selection of the data path with optimal phase alignment can be achieved by tracking the phase delay variation over the entire packet length and making necessary changes to the 4:1 selector on-the-fly. Reconfiguring the 4:1 selector during the middle of data transmission is expected to introduce negligible penalty since the selector (HMC958LC5) can support a maximum select rate of 14 GHz. IV. CONCLUSION A 10Gbps burst-mode clock and data recovery (BM-CDR) circuit based on phase picking method is presented. Experiment demonstrates the proposed BM-CDR circuit is able to align the burst mode incoming packets to the local clock with a maximum phase misalignment of ±π/8 within 20 ns. REFERENCES      Figure 7. Recorded scope traces and RMS Jitter by Agilent 86100A. Top: reference clock, Bottom: extracted clock. The Q of the BPF is 200. S. J. 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