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Power MOSFETs(5)
2013.01.22
SD Lab. SOGANG Univ.
Doohyung Cho
SOGANG
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UNIVERSITY. SEMICONDUCTOR DEVICE LAB.
Contents
•
•
6.17.1 Bipolar Second Breakdown
6.17.2 MOS Second Breakdown
•
•
6.18.1 Reverse Recovery Enhancement
6.18.2 Impact of Parasitic Bipolar Transistor
•
•
•
6.19.1 Threshold Voltage
6.19.2 On-Resistance
6.19.3 Saturation Transconductance
•
•
•
6.20.1 The p-Channel Structure
6.20.2 On-Resistance
6.20.3 Deep-Trench Structure
•
•
6.21.1 Planar VD-MOSFET Process
6.21.2 Trench U-MOSFET Process
•
•
•
•
6.22.1
6.22.2
6.22.3
6.22.4
6.18 Integral Body Diode
6.19 High-Temperature Characteristics
6.20 Complementary Devices
6.21 Silicon Power MOSFET Process Technology
6.22 Silicon Carbide Devices
The Baliga-Pair Configuration
Planar Power Structure
Shielded Planar Power MOSFET Structure
Shielded Trench-Gate Power MOSFET Structure
6.23 Summary
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6.17.1 Bipolar Second Breakdown
•
The lateral current flow path through
the P-base region produces a forward
bias across the emitter–base junction of
the parasitic bipolar transistor at
location A.
•
The drain bias at which the emitter
current becomes very large can be
obtained.
The bipolar second breakdown mode
can be suppressed by reduction of the
P-base resistance with the addition of a
P+ region
•
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6.17.2 MOS Second Breakdown
• The voltage drop across the P-base resistance due to the avalanche
breakdown induced current produces a body bias effect
• The MOS second breakdown mode can also be suppressed by
reduction of the Pbase resistance with the addition of a P+ region
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6.18 Integral Body Diode
• The primary difficult with utilization of the integral diode in the power
MOSFET structure is its poor reverse recovery characteristic due to the high
lifetime in the N-drift region. In addition, the presence of the N+ source
region can lead to the turn-on of the parasitic N–P–N bipolar transistor
during the reverse recovery transient leading to destructive failure
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6.18.1 Reverse Recovery Enhancement
• Methods for reducing the lifetime consist of the addition of deep level
centers such as gold or platinum or by the use of high energy particle
bombardment
• The application of these techniques to the power MOSFET structure is
hindered by the degradation of the gate oxide and its interface properties
with the silicon.
• it was discovered that this oxide charge can be removed by annealing the
devices at relatively low temperatures
• Electron irradiation provides a clean and precise process for improving the
reverse recovery behavior of the integral diode without compromising any
of the power MOSFET device characteristics.
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6.18.2 Impact of Parasitic Bipolar Transistor
• The drain blocking voltage during the reverse recovery transient can exceed
the open-base breakdown voltage of the parasitic N–P–N transistor resulting in
destructive failure
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6.19 High-Temperature Characteristics
• Power MOSFET structures have superior high-temperature operating
capability when compared with bipolar devices with the same voltage
ratings. Commercial devices are available with a maximum junction
temperature capability of up to 200°C.
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6.19.1 Threshold Voltage
• The threshold voltage for power MOSFET structures decreases with
increasing temperature due to the increase in the intrinsic carrier
concentration.
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6.19.2 On-Resistance
• The on-resistance of power MOSFET structures is observed to increase
with increasing temperature. This is attributed to the reduction of the
mobility in the drift region and the inversion layer
• The increase in the on resistance due to the increased temperature favors
a redistribution of the current to other locations within the device. This
prevents the formation of “hot spots”
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6.19.3 Saturation Transconductance
• The temperature-dependent terms in this
expression are the channel mobility and
the threshold voltage.
• The net result is a reduction of the
transconductance with increasing
temperature
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6.20 Complementary Devices&6.20.1 The p-Channel Structure
• all the bias voltages must be changed from positive to negative
values for the p-channel structure
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6.20.2 On-Resistance
• The components of the on-resistance for the p-channel structure are
identical to those for the corresponding n-channel structure. However, the
magnitude for the specific on-resistance for the various components is larger
in the p-channel structure due to the lower mobility for holes than electrons
in silicon.
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6.20.3 Deep-Trench Structure
• deep-trench architecture, the trench is
extended from the upper surface into the
N+ or P+ substrate. When the gate bias is
applied to turn on the device, an inversion
layer is formed along the trench sidewalls
within the base region extending all the
way from the source to the drain region
• allowing a reduction of the specific on
resistance due to elimination of the drift
region component
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6.21 Silicon Power MOSFET Process Technology
• V-groove process (1970s) - with the sharp point of the V-groove gate
structure and instabilities associated with the potassium hydroxide-based
etching solutions.
• VD-MOS process(1980s) - utilization of improved design rules to reduce the
size of the diffusion window leading to a lower specific on-resistance.(BUT
presence of JFET)
• U-MOS process(1990s) - availability of reactive ion etching (RIE),
achievement of lower specific on-resistance
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6.21.1 Planar VD-MOSFET Process
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6.21.2 Trench U-MOSFET Process
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6.22 Silicon Carbide Devices
• The Baliga’s figure of merit for 4H-SiC is more than 2,000 times superior to that
for silicon.
• First, the quality of the interface between the thermally grown oxide and the
silicon carbide surface has been poor resulting in low inversion layer mobility.
• Second, the high electric field generated within the silicon carbide produces
very high electric field within the gate oxide leading to its rupture during
operation.
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6.22.1 The Baliga-Pair Configuration
• In the Baliga-Pair configuration, a low
breakdown voltage, normally-off, silicon
MOSFET and a high-voltage, normally-on,
silicon carbide JFET/MESFET are connected
together
• It is important that the silicon carbide FET
structure be designed for normally-on
operation with a low specific on-resistance.
It is also necessary for the silicon carbide
FET to be able to block the drain bias
voltage with a gate potential less than the
breakdown voltage of the silicon power
MOSFET.
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6.22.1 The Baliga-Pair Configuration
Voltage Blocking Mode
•
as the voltage at the drain (DM) of the silicon
MOSFET increases, an equal positive voltage
develops at the source (SSiC) of the silicon carbide
FET. Since the gate (GSiC) of the silicon carbide FET
is connected to the ground terminal, this produces
a reverse bias across the gate–source junction of
the silicon carbide FET
•
When the depletion region pinches off the channel
at location A, further increase in the bias applied
to the drain (DB) of the composite switch is
supported across the silicon carbide FET.
•
value close to the pinch-off voltage of the silicon
carbide FET.
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6.22.1 The Baliga-Pair Configuration
Forward Conduction Mode
•
Due to the low specific on-resistance of both
structures, the total on resistance of the Baliga-Pair
configuration is also very small.
Current Saturation Mode
•
Due to the low specific on-resistance of both
structures, the total on resistance of the Baliga-Pair
configuration is also very small.
•
Baliga-Pair behaves like a silicon power MOSFET
from the point of view of the external circuit on
both the input and output side(safety device)
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6.22.1 The Baliga-Pair Configuration
Switching Characteristics
•
The switching speed of the Baliga-Pair is
consequently very high because of the availability
of silicon power MOSFETs designed for high
frequency applications.
Fly-back Diode
•
The Baliga-Pair contains an inherent high-quality
fly-back rectifier. When the drain bias is reversed
to a negative value, the gate–drain
contact/junction of the silicon carbide FET
becomes forward biased.
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6.22.2 Planar Power Structure
• The diffusion rate for dopants is extremely small in silicon carbide even at
very high temperatures
• together with the location of the ion implantation edges. These devices
have been called DIMOSFETs because of the double-implant process used
for their fabrication
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6.22.2 Planar Power Structure
Blocking Characteristics
•
large leakage current can occur when the depletion
region in the P-base region reaches through to the
N+ source region. The doping concentration and
thickness of the P-base region must be designed to
prevent the reach-through phenomenon from limiting
the breakdown voltage.
•
At any given P-base doping concentration, the
thickness for 4H-SiC is about six times larger than for
silicon. This implies that the minimum channel length
required for silicon carbide devices is much larger
than for silicon devices, resulting in a big increase in
the on-resistance.
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6.22.2 Planar Power Structure
Threshold Voltage
• The much larger threshold voltage for silicon
carbide is physically related to its larger band
gap (which results in an extremely small
value for the intrinsic concentration in (6.282))
as well as the higher P-base doping
concentration required to suppress reachthrough breakdown.
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6.22.2 Planar Power Structure
Oxide Field
• maximum electric field in the silicon drift
region remains below 3 × 105 V cm−1, the
electric field in the oxide does not exceed its
reliability limit of about 3 × 106 V cm−1.
However, for 4H-SiC, the electric field in the
oxide reaches a value of 9 × 106 V cm−1
• important to monitor the electric field in the
gate oxide when designing and modeling the
silicon carbide MOSFET structures.
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6.22.2 Planar Power Structure
Oxide Field
• This leads to hot electron injection-induced
instability of the threshold voltage.
• The trapping of these electrons within the gate
oxide can cause shifts in the threshold voltage
of the MOSFET leading to reliability problems.
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6.22.3 Shielded Planar Power MOSFET Structure
Blocking Mode
• fully utilize the high breakdown electric field strength available in silicon
carbide, it is important to screen the gate oxide from the high field within the
semiconductor
• this is achieved by the formation of a potential barrier at location A by the
depletion of the JFET region at a low drain bias voltage.
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6.22.3 Shielded Planar Power MOSFET Structure
Threshold Voltage
• declining influence of the P+/N junction at the gate oxide interface when the
doping concentration of the N-base region is increased
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6.22.4 Shielded Trench-Gate Power MOSFET Structure
Blocking Characteristics
• high electric field can develop in the N-drift
region below the P+ shielding region while
the electric field at the Pbase region remains
low.
• sheet resistance of the ion-implanted P+
region can be quite high
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6.22.4 Shielded Trench-Gate Power MOSFET Structure
Forward Conduction
• first one, labeled RJFET1 in the figure, is
formed between the P-base region and the
P+ shielding region with the current
constricted by their zero-bias depletion
boundaries.
• second JFET region, labeled RJFET2 in the
figure, is formed between the P+ shielding
regions. Its resistance is determined by the
thickness of the P+ shielding region
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6.22.4 Shielded Trench-Gate Power MOSFET Structure
Forward Conduction
• It can be seen that the drift region resistance is dominant here while the JFET
resistances are very small.
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6.23 Summary
• especially for devices designed to support low blocking voltages. Since the specific
on-resistance now approaches the ideal value, further improvements in the
performance of power MOSFET devices have focused on reduction of the input
gate capacitance and the gate charge.
• 4H-polytype. With 4H-SiC, it is possible to reduce the specific on-resistance by
over a factor of 1,000 times in switches designed for operation at above 1,000 V.
• The commercialization of this technology is expected to result in improvements in
the size, weight, and efficiency of high power electronic systems in the future.
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