Download A 43-GHZ STATIC FREQUENCY DIVIDER IN 0.13µM STANDARD

A 43-GHZ STATIC FREQUENCY DIVIDER IN 0.13μM STANDARD CMOS
Bangli Liang, Dianyong Chen, Bo Wang, Dezhong Cheng, Tad Kwasniewski
Department of Electronics, Carleton University, 1125 Colonel By Dr., Ottawa, ON, K1S 5B6, Canada
ABSTRACT
In this paper, a low supply static 2:1 frequency divider
based on 0.13μm CMOS is presented. It is designed for 40Gb/s optical communication systems. Current-mode logic
(CML) is adopted because of the higher speed compared to
static CMOS and the robustness against common-mode
disturbances. This frequency divider is designed with output
buffer to drive the external 50Ω loads. On-chip shunt
peaking (SP) inductors and split-resistor (SR) loads are used
to boost the bandwidth. The frequency divider uses a single
1.2-V supply voltage and consumes a total current of 32mA.
And the chip area is only 0.63mm2 with bonding pads.
The proposed 2:1 frequency divider shown in Fig.1 consists
of a master-slave flip-flop (MS-FF) with feedback from its
output to its input and a 3-stage output buffer (BUFF),
which provides better signal waveform, appropriate
amplitude, proper DC level and good output matching.
DP
DN
Input
CKP
CKN
QP
QN
BUFF
MS-FF
Output
Buffer
Index Terms—CML, frequency divider, SP, SR
Fig.1. Block diagram of the 2:1 frequency divider.
1. INTRODUCTION
VDD
Today`s serial data communication systems operate at bit
rates between 10- and 40-Gb/s. Current communication ICs
are mainly implemented in GaAs, InP, or SiGe bipolar
technologies. Some high-speed chips in CMOS technologies
are reported in [1]-[6], which confirm CMOS to be a viable
alternative for broadband circuit design because advanced
circuit techniques and a state-of-the-art fabrication process
can be combined to extend speed limits. This approach is
very economical due to the lower production costs, higher
yield, and integration density.
As a key block in data communication systems, current
CMOS frequency divider already achieve speeds higher
than 20-GHz [1]-[6]. In this work, a 43-Gb/s 2:1 frequency
divider in IBM 0.13μm CMOS is presented. The
manufactured nMOS transistors have a ft of 100 GHz. All
subcircuits of this frequency divider use current-mode logic
(CML) with differential signals. Compared to conventional
static CMOS logic, CML circuits employ reduced internal
voltage swings, which is essential for high switching speeds
[7]. To reach the operating frequency of 40GHz, the
proposed frequency divider uses SP spiral inductors and SR
loads to boost the bandwidth.
CLK_OUT
CLK_IN
7mA
LVT
7mA
RVT
VSS
(a) Traditional frequency divider
VDD
CLK_OUT
CLK_IN
7mA
7mA
RVT
VSS
2. CIRCUITS DESIGN
(b) Frequency divider with SP
CCECE/CCGEI May 5-7 2008 Niagara Falls. Canada
978-1-4244-1643-1/08/$25.00 ” 2008 IEEE
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LVT
level. The last differential amplifier using SP loads is
designed to provide enough bandwidth, driving capability
and good matching to external load.
VDD
CLK_OUT
CLK_IN
7mA
LVT
7mA
RVT
VSS
(c) Frequency divider with SP and SR
VDD
OUT
(a) High Q-value thick metal spiral inductors
IN
LVT
RVT
2.5mA
5mA
10mA
VSS
(d) Output buffer
Fig.2. The schematic of three frequency divider topologies
and output buffer.
The MS-FF in Fig. 2 (a)-(c) consists of two latches
connected in series. The clock of one latch is in phase while
the other one is inverted. All transistors of the frequency
divider are nMOS devices because of their higher speed
compared to pMOS transistors. All transistors in the core are
low-VT 120nm nMOS devices for low supply (1.2V or less)
operating. The latches use series gating between clock and
data inputs. All data path transistors are 2/15 the width of
the clock transistors to reduce the parasitic capacitance at
the output nodes of latches and to make the clock pairs
switch more easily. Especially, the size of transistors in
holding branches is slightly smaller than the size of those in
sampling branches to speed up the sampling-holding
process. Poly-silicon resistors (100) with SR topology (R1
and R2 are separated by output node) are used as loads to
reduce parasite capacitances and Miller Effect, which is a
compromise between high internal voltage swing (DC gain)
and reasonable RC time constant. Clock input matching is
realized with poly-silicon resistors and spiral inductors,
which are connected to a DC level shifter (0.6VDD). The tail
current of both latches is set to 7mA.
The output buffer showed in Fig. 2 (d) consists of three
common-source amplifiers in series. The first stage offers a
high-voltage swing of 600mV, which drives the second
stage. The second stage works as a limiting amplifier to
provides appropriate amplitude, proper common-mode
(b) Characteristic of four types of current source
Fig.3. Passive and active devices based on CMOS process.
To achieve very high operating frequency and low phase
noise, SP are implemented via using on-chip spiral inductors
with high Q-value as shown in Fig.3 (a).
Both the proposed latches and output buffer employ
stacked current sources to achieve higher output impedances
and more stable DC operating points as shown in Fig.3 (b),
which is a little bit better than cascode current mirror and
requires less transistors and no extra DC bias. In addition,
stacked LVT and regular-VT (RVT) nMOS transistors with
a channel length of 180nm are used as current source to
reduce short channel effects and geometric mismatches.
The designed frequency divider is integrated in the area
of 0.7×0.9mm2. The layout is shown in Fig. 4. It is devised
to be maximally symmetrical to keep the circuit as balance
as possible for high immunity against common-mode
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disturbances. Input signal path and output signal path are
routed perpendicularly to lower crosstalk. ‘PGSGP’ and
‘SGS’ pads patterns are used for high symmetry, low
disturbance and easy on-chip test.
greatly improve the operating speed of CML circuits up to
50%.
(a) VDD=1V
Fig.4. The layout of the 2:1 frequency divider.
(b) VDD=1.2V
Fig.5. Simulated input sensitivity curves of three frequency
divider topologies: V1⎯Traditional frequency divider;
V2⎯Frequency divider with SP; V3⎯Frequency divider
with SP and SR.
3. CIRCUIT SIMULATIONS AND RESULTS
To verify this design, circuit simulations are carried out
using the Cadence simulator Spectre and BSIM4 model of
IBM 0.13μm CMOS technology.
Simulated input sensitivity curves and self-oscillation
frequencies and amplitudes of three frequency divider
topologies operating under 1.2V supply are given in Fig. 5.
The frequency divider with SP and SR (V3) operates at the
highest frequency of 43.2 GHz, which confirms that the
employed on-chip spiral SP inductors and SR loads can
(c) VDD=1.5V
Fig.6. Starting self-oscillations of the frequency divider with
SP and SR under different supply voltages.
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amplitude. Based on Fig. 6-7, the employed stacked current
sources offer very good immunity to supply fluctuations.
Simulation results of the proposed frequency divider (V3)
and the comparison to previous work are given in Table 1.
The designed frequency divider (V3) can operate under
lower supply and consume lesser power.
4. CONCLUTIONS
A fully integrated 0.13μm CMOS frequency divider with SP
and SR was presented. In this design, an additional design
parameter, the ratio of R1/R2 in the used SR loads is
introduced to provide a trade-off between high voltage
amplitude and small RC time constant. Through optimizing
the ratio of R1/R2, the proposed frequency divider exhibits
an operating frequency of 43GHz and consumes a power of
38mW under a 1.2V supply. The chip size is only 0.63mm2.
It is designed to be used in 40-Gb/s optical communication
systems.
(a) Input signal
5. REFERENCES
[1] G. von Büren, C. Kromer, F. Ellinger1, A. Huber, M. Schmatz,
H. Jäckel, “A Combined Dynamic and Static Frequency
Divider for a 40GHz PLL in 80nm CMOS,” IEEE Int. Conf.
Solid-State Circuits, Dig. Tech. Papers, Feb., 2006, pp. 2462 –
2471.
[2] J. Lee and B. Razavi, “A 40GHz Frequency Divider in 0.18μm
CMOS Technology,” IEEE J. Solid-State Circuits, vol. 39, pp
594-601, Apr., 2004
[3] U. Singh and M. M. Green, “High-Frequency CML Clock
Dividers in 0.13μm CMOS Operating Up to 38GHz,” IEEE J.
Solid-State Circuits, vol. 40, no.8, pp.1658-1661, Aug. 2005.
(b) Output signal
[4] H. -D. Wohlmuth and D. Kehrer, “A High Sensitivity Static 2:1
Frequency Divider up to 27 GHz in 120 nm CMOS,” in Proc.
Eur. Solid State Circuits Conf. (ESSCIRC), Sept. 2002, pp.
823–826.
Fig.7. Transient analyses of the frequency divider with SP
and SR operating at 40GHz.
Table 1 Comparison with previous work
Ref.
[1]
[2]
[3]
[4]
[5]
This
Supply
(V)
1.1
2.5
1.8
1.5
1.2-1.5
1.0-1.5
fmax
÷N
Power
41
40
38
27
24-25
38-44
4
4
2
2
2
2
2.2(core)
31
12
45
37-61
27-60
[5] H. Knapp, H.-D. Wohlmuth, M. Wurzer and M. Rest, “25GHz
Static Frequency Divider and 25Gb/s Multiplexer in 0.12μm
CMOS,” in IEEE Int. Solid State Circuits Conf. Dig. Tech.
Papers, Feb. 2002, pp.302-468.
Technology
CMOS
80nm
0.18μm
0.13μm
0.13μm
0.13μm
0.13μm
[6] M.M.Green and U. Singh, “Design of CMOS CML circuits for
high speed broadband communications,” in Proc. ISCAS, May
2003, pp. 25–28.
Fig. 6 shows the transient self-oscillation waveforms of
the frequency divider (V3) under different supply voltages.
It can be seen that the frequency divider operates at higher
frequency and larger output swing under a higher supply
with the price of more power dissipation. Fig. 7 illustrates
that the frequency divider with SP and SR can operate at
40GHz with good voltage waveform and enough signal
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