Download HW10 - Iowa State University

Name:
Lab Section:
CprE 288 Spring 2017 – Homework 10
Due: Friday, April 14, 11.00 PM (on Blackboard)
Instructions:
 Homework is individual work. Adhere to the University’s policy relating to the integrity
of scholarship. See
http://catalog.iastate.edu/academic_conduct/#academicdishonestytext
(“Academic Dishonesty”).
 Homework must be typed and uploaded to BlackBoard as a PDF or Word Document (i.e.
.doc or .docx) only.

NO Late homework will be accepted.

Submission link will be available for 30 min (grace period) after 11.00 PM and will
become invisible at 11.30 PM.

Three attempts will be allowed for submission of homework. Last submitted work will
be graded.
 Note: Code that will not compile is a type-O. Answering a question as “will not compile”
will be marked incorrect. Contact the Professor if you think you have found a type-O.
Note: Unless otherwise specified, all problems assume the TM4C123 is being used.
1) Instruction Set Basics [12 pts]
a) What is the difference between ARM Instruction set, Thumb instruction set and Thumb-2
instruction set (as discussed in class) ? Explain. [2 pts]
b) What are the primary tradeoffs in mixing 16-bit and 32-bit instructions in Thumb-2
instruction set (as discussed in class) ? Explain. [2 pts]
c) What are the main differences between CISC and RISC instruction set architectures ?
Explain the motivation for the differences in your answer. [2 pts]
d) Is ARM instruction set architecture - RISC or CISC ? Explain. [2 pts]
Name:
Lab Section:
e) Thumb-2 designers chose to have variable length instructions, though ARM embraces RISC
design philosophy. Why do you think Thumb-2 variable length makes sense? Explain your
answer. [2 pts]
f) Does variable instruction set have negative impact on TM4C123 performance? Explain your
answer. [2 pts]
2) Cortex-M4 Instruction Set – General Info. [10 pts]
a) Briefly explain the four fields in Cortex-M4 assembly language syntax? See Section 4.3.1 in
Textbook. [2 pts]
b) Why should Bit0 = 1 for any address written to the PC register with a BX, BLX instruction?
[2 pts]
c) What is Unified Assembly Language ? [1 pt]
d) List the 7 addressing mode in Cortex-M4 instruction set. Give one example assembly
instruction for each addressing mode. See Section 4.3.3 in Textbook. [5 pts]
3) Cortex-M4 Instruction Set – Instruction class [6 pts]
a) What is the difference in the functionality between STR R5, [R7], #4 and STR R5,
[R7,#4]! ? [1 pts]
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Lab Section:
b) MOV is encoded as a 16-bit instruction, why must MOVW be encoded as a larger than 16-bit
instruction? [1 pts]
c) Using the “ARM Instruction Set Manual”, give the general binary encoding for STR Rt,
[Rn, #Imm8]! and the specific binary encoding for and STR R5, [R7,#4]! [2 pts]
i) General binary encoding [1pts]:
ii) Specific binary encoding [1pts]:
d) Using the “ARM Instruction Set Manual”, give the general binary encoding for MUL Rd,
Rn, Rm and the specific binary encoding for MUL R8, R10, R9 [2 pts]
i) General binary encoding [1pts]:
ii) Specific binary encoding [1pts]:
4) Fill the final vales of the Register file and Data memory after the following
assemble code has been executed. Vales in ( ) are the initial values before the
assemble code is executed. Show temporary values to help with giving partial
credit, and if an entry is unknown after executing the code then leave blank.
Part a and part b are independent of each other [10 pts]
a) 5 pts
MOVW R10, 0xFFF4
MOVT R10, 0xFFFF
LDR R0, [R10], #4
ANDS R0, 0x0077FF
STR R0, [R10, #0]
Name:
Lab Section:
Register File
Reg
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Value
b) 5 pts
MOVW R9, 0xFFF0
MOVT R9, 0xFFFF
MOVW R6, 0x10
MOVW R7, 0x10
LDR R2, [R9], #4
LDR R3, [R9, #4]
ADDS R2, R9
STR R2, [R9, #4]!
SUBS R6, R7
BEQ my_label
MOVW R6, 0x20
my_label:
MOVW R7, 0x30
Data Memory
Address
0xFFFF_FFFF
0xFFFF_FFFE
0xFFFF_FFFD
0xFFFF_FFFC
0xFFFF_FFFB
0xFFFF_FFFA
0xFFFF_FFF9
0xFFFF_FFF8
0xFFFF_FFF7
0xFFFF_FFF6
0xFFFF_FFF5
0xFFFF_FFF4
0xFFFF_FFF3
0xFFFF_FFF2
0xFFFF_FFF1
0xFFFF_FFF0
Value
(0xF4)
(0x0A)
(0x07)
(0x03)
(0x01)
(0x04)
(0xC0)
(0xFF)
Name:
Lab Section:
Register File
Reg
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Data Memory
Address
0xFFFF_FFFF
0xFFFF_FFFE
0xFFFF_FFFD
0xFFFF_FFFC
0xFFFF_FFFB
0xFFFF_FFFA
0xFFFF_FFF9
0xFFFF_FFF8
0xFFFF_FFF7
0xFFFF_FFF6
0xFFFF_FFF5
0xFFFF_FFF4
0xFFFF_FFF3
0xFFFF_FFF2
0xFFFF_FFF1
0xFFFF_FFF0
Value
Value
(0xAA)
(0xF7)
(0xF4)
(0x0A)
(0x07)
(0x03)
(0x01)
(0x04)
(0xC0)
(0xFF)
(0x22)
(0xCC)
5) (Assembly Practice) [12 pts].
// Variable declaration assumptions
unsigned
unsigned
unsigned
unsigned
char
char
char
*pch
A[5];
ch1 = 2;
ch2 = 3;
= &ch2;
// Assume the following memory locations:
// located at 0xFFFF_F800
// located at 0xFFFF_F900
// located at 0xFFFF_FA00
// located at 0xFFFF_FB00
unsigned int a = 0x10FF; // located at 0xFFFF_FC00
unsigned int b = 0x80FF; // located at 0xFFFF_FD00
unsigned int *pint = &b; // located at 0xFFFF_FE00
Name:
Lab Section:
For the assumptions given for the declared variables, write the assembly code to implement
each functionality. Each question is independent.
a. Arithmetic [2 pts]
a = b + 1;
b. Logic [2 pts]
ch1 = ch1 | ch2;
c. Initialize a pointer [2 pts]
pch = &ch1; //Hint: the address of a variable in C is constant
d. Copy variables using a pointer [2 pts]
*pint = b;
e. Set an Array element to a deferenced pointer [2 pts]
A[4] = (*pch) + 1;
f. Multiplication [2pts]
a = a * b;
Name:
Lab Section: