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2323 Cloverdale Rd
Naperville, IL
(630) 536-8122
[email protected]
Engineering professional with over 20 years of experience in development of FPGAs and ASICs. Employ a diverse set of
skills including design, verification, lab validation, debug, embedded software, and system test to produce complex systems
on time and cost effectively. Utilize experience to provide effective project leadership, vendor management, and decision
making with consideration toward the technical and business needs of the project. Work effectively with Marketing,
Hardware, Software, and Manufacturing to ensure delivery of products that meet all requirements.
- Excellent understanding of Altera and Xilinx devices and tools
- RTL design using all widely used HDL languages, VHDL, Verilog, and SystemVerilog
- Simulation, synthesis, static timing, place & route, timing closure
- Test Plan, self-checking Test Benches, and Model generation
- Validation and debug of devices in lab environment
- Embedded software development for FPGA support and system test
- Team leadership, vendor management, development of tools & methodologies
Design Tools:
Altera Quartus, Xilinx ISE/Vivado, Actel Libero IDE/SOC
Mentor Modelsim/HDL Designer, Synopsys VCS/SynplifyPro
VHDL, Verilog, SystemVerilog, SDC, C, TCL/Expect, HTML, Linux shell scripting
Business Tools: MS Word, MS Visio, MS Excel, MS PowerPoint, MS Project, Clearcase, ClearQuest
2002 – 2013
Tellabs, Naperville, IL
Staff Engineer
Designed and tested many FPGAs within Tellabs large edge router, large cross-connect, and small wireless backhaul boxes.
Worked on wide variety of projects including FPGA, Embedded Software, and System Test. All device designs included
requirements and specification development. Maintained Linux server farm, tools, and methodologies used in FPGA
development. Apply knowledge to deliver ASIC quality FPGAs.
Xilinx Virtex 5 Switch Fabric Gateway FPGA. Utilized custom application of 8b10b characters to obtain byte, word, and
cell alignment on the SerDes interface. Responsible for full-chip simulation, synthesis, and place & route. Developed
unique SynplifyPro multi file environment of constraints, allowing block level designers to deliver constraints file that
automatically integrated into full-chip synthesis.
Xilinx Virtex 5 PCI Express Endpoint interface that was both a completer and initiator. Employed two FSMs with a
FIFO in between to track transmitted requests and their returned completions. Design accessed ring structures in CPU’s
main memory and provided configuration of FPGA.
Altera Stratix V design with PCIe, SPI4, and high speed SerDes. Because device did not have enough SerDes IO with
hard PCS, developed soft PCS for CMU only channels. To improve design time, worked jointly with team member on
complex packet reassembly block utilizing external QDRII.
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Michael J. O’Brien
[email protected]
Xilinx Kintex 7 with multiple high speed serial interfaces. 10 Gig Ethernet interfaces, using 10GBASE-R and XAUI,
and PCI Express. Modified generated RTL and SDC constraints to allow all SerDes modules to co-exist. To improve
performance, utilized new Vivado tool suite rather than ISE. AXI4 protocol to interface to IP modules.
SW application to intelligently upgrade or downgrade one or more FPGA multi-boot images in SPI Flash. At first HW
was not available, so developed functions in System Verilog and simulated using behavior models. Converted
SystemVerilog to C for embedded software and debugged using Wind River ICE2 debugger. Wrote TCL scripts to
automate execution of updates in the labs and field.
Actel SOC reference design used as ATCA IPMC device in Tellabs Smart Router. Modify, compile, and verify
firmware running on embedded ARM core.
Xilinx Spartan 3A design enhancement to facilitate factory testing of system timing ports. Creatively modified small
PCBs inside custom SFPs used in factory to test GE Optical Interfaces. Allowed factory to test SFP IO that was
previously untested. Developed TCL scripts to allow quick and repeatable testing of initial prototypes.
Altera Cyclone IV design deserialized multiple E1/T1 streams to feed into common frame structure. Serialized frame
structure for transmission between two Cyclone IV devices via custom SerDes application using simple framing protocol
utilizing 8b10b comma characters. Project included TCL scripting for lab validation, which made validation repeatable
and self documenting.
AES decryption block for GPON ONT FPGA.
ASIC design of several large devices for new products. Lead Architect of RTL design for STS-48 Framer, mentoring
less experienced designers. Performed block level floor-planning, place, and route for framer ASIC. Lead verification
engineer of Quad Mapper ASIC.
Tellabs, Naperville, IL
Development Manager
1998 - 2002
Managed multiple ASIC projects concurrently, while providing technical leadership, mentoring, and ASIC process
methodology. Projects included use of COT process and out sourcing the back-end. Managed highly diverse internal and
external teams, resolving conflicts while instilling strong team spirit, delivering on time with no major problems. These were
SONET and ATM ASICs used in the Tellabs high bandwidth cell based switch.
Tellabs, Naperville, IL
Lead Engineer, Senior Member of Technical Staff, Member of Technical Staff
1990 - 1998
Worked on several ASICs for large cross-connect. Developed strong understanding of system requirements; becoming a
leader in design, requirements, and specifications for the devices. Performed all parts of ASIC design flow including design,
synthesis, functional simulation, test logic/vector generation (ATPG), floor planning, physical place & route, DRC/LVS,
static timing, timing simulation, and prototype characterization on HP IC tester.
Bachelor of Science in Electrical Engineering (BSEE), Purdue University, W. Lafayette, IN
Course work completed toward MBA in Project Management at Keller Graduate School 2003-2004
Recipient of Tellabs Key Contributor Awards
Recipient of Tellabs Top Performance Bonus Award
Recipient of Tellabs Corporate Award
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