Download Sep 2001 New 16-Bit 50Msps DAC Offers Highest AC and DC

LINEAR TECHNOLOGY
SEPTEMBER 2001
IN THIS ISSUE…
COVER ARTICLE
New 16-Bit 50Msps DAC Offers
Highest AC and DC Performance ... 1
James L. Brubaker and William C. Rempfer
Issue Highlights ............................ 2
LTC® in the News ........................... 2
DESIGN FEATURES
A Thermoelectric Cooler Temperature
Controller for Fiber Optic Lasers ... 5
Jim Williams
®
LT 1681 and LTC1698 Team Up to
Provide a Complete Solution
for 48V Input, 2-Transistor
Synchronous Forward Converters
..................................................... 9
Kurk Mathews
High Efficiency, Low Cost Power
Supply Meets Intel Mobile Voltage
Positioning Requirements ............ 13
Wei Chen, Peter Guan and David Chen
Two New Switching Regulators
Deliver Both Power
and Ultralow Noise ...................... 18
Rick Brewster
Adjustable Low-Battery Threshold
Detector Extends Battery Runtime
................................................... 21
VOLUME XI NUMBER 3
New 16-Bit 50Msps DAC
Offers Highest AC and
DC Performance
by James L. Brubaker and William C. Rempfer
New 16-Bit 50Msps DAC
Block Diagram and Function
The new LTC1668 is a 16-bit, 50Msps,
differential current output DAC with
exceptional AC and DC performance.
Spurious free dynamic range (SFDR)
of greater than 87dB, glitch impulse
of <4pV-s, 18ns full-scale settling time
(to 0.1%) and 1LSB DNL and 3LSB
INL (typical) provide the highest combination of AC and DC specifications
available. The LTC1668 is part of a
pin-compatible family that includes
the 14-bit LTC1667 and the 12-bit
LTC1666.
Referring to Figure 1, the LTC1668
has a 16-bit parallel input, an internal reference and differential 10mA
full-scale current outputs. It runs on
a ±5V supply and dissipates 180mW.
The DAC contains an array of current
sources that are steered to IOUTA or
IOUTB with NMOS differential current
switches. The four most significant
5V
0.1µF
25
Brendan Whelan
1.2MHz ThinSOT™ Boost Converter
Operates from a Single Cell,
Saves Board Space and Delivers
93% Efficiency ............................ 23
VREF
15
REFOUT
2.5V
REFERENCE
0.1µF
John Bazinet
16
IFS/8
+
IINT
21
0.1µF
22
IOUT A
20
+
IOUT B
19
–
VOUT
1VP-P
DIFFERENTIAL
•••
•••
COMP1
INPUT LATCHES
COMP2
New Device Cameos ..................... 37
Sales Offices ............................... 40
18
CURRENT SOURCE ARRAY
–
DESIGN IDEAS
.............................................. 31–36
52.3Ω
×2
LADCOM
SEGMENTED SWITCHES
FOR DB15–DB12
LSB SWITCHES
IREFIN
Tick Houk
Design Tools ................................ 39
ATTENUATOR
LADDER
RSET
2k
The LTC1871 Achieves the Industry’s
Highest Efficiency for Single-Ended
Boost, Flyback and SEPIC Topologies
................................................... 26
(complete list on page 31)
continued on page 3
VSS
0.1µF
–5V
23
0.1µF
AGND
DGND
17
24
CLK
26
DB15
•••
27
DB0
14
•••
CLOCK
INPUT
16-BIT
DATA INPUT
Figure 1. LTC1668 block diagram
, LTC and LT are registered trademarks of Linear Technology Corporation. Adaptive Power, Burst Mode, C-Load,
DirectSense, FilterCAD, Hot Swap, LinearView, Micropower SwitcherCAD, Multimode Dimming, No Latency ∆Σ,
No RSENSE, Operational Filter, OPTI-LOOP, Over-The-Top, PolyPhase, PowerSOT, SwitcherCAD, ThinSOT and UltraFast
are trademarks of Linear Technology Corporation. Other product names may be trademarks of the companies that
manufacture the products.
DESIGN FEATURES
5V
0.1µF
REFOUT
RSET
2k
0.1µF
VDD
2.5V
REFERENCE
LTC1668
MINI-CIRCUITS
T1–1T
IREFIN
IOUT A
+
16-BIT
HIGH SPEED
DAC
–
110Ω
IOUT B
COMP1
C1
0.1µF
50Ω
50Ω
LADCOM
COMP2
AGND DGND
VSS
C2
0.1µF
TO HP3589A
SPECTRUM
ANALYZER
50Ω INPUT
CLK
DB15
DB0
16
0.1µF
DIGITAL
DATA
– 5V
CLK
IN
OUT 1 OUT 2
HP8110A DUAL
PULSE GENERATOR
HP1663EA
CLK
LOGIC ANALYZER WITH
IN
PATTERN GENERATOR
LOW JITTER
CLOCK SOURCE
Figure 2. AC characterization setup
LTC1668, continued from page 1
bits (DB15–DB12) are segmented into
fifteen equal currents. The lower bits
(DB11–DB0) are binary weighted
using a combination of current scaling and a differential resistive
attenuator ladder.
The DAC has an internal 2.5V reference. The full-scale DAC output
current, IOUTFS, is set by a resistor
(RSET) between REFOUT and IREFIN.
(For IOUTFS of 10mA, RSET is 2k.)
The digital inputs can accept CMOS
levels from either 3V or 5V logic and
can be clocked at up to 50Msps. They
are latched on the rising edge of the
clock input, CLK.
The differential current outputs
have a compliance range of ±1V and
may be used in single-ended or differential configurations. The outputs can
be converted to a voltage by resistor
loading, transformer coupling or by
using an op amp current-to-voltage
converter.
Best AC and Frequency
Domain Performance
The LTC1668 offers the best frequency
domain performance available today.
It excels with single-tone and multitone signals at full scale and even
with reduced amplitude signals.
Single-Tone Spurious Free
Dynamic Range (SFDR)
Figure 2 shows the AC characterization setup used for the LTC1668.
Figure 3 shows the single tone SFDR
at 50Msps with a 1MHz output signal. The signal amplitude is 0dBFS
(that is, a full-scale digital sine wave)
2-Tone Spurious Free Dynamic
Range (SFDR)
Figure 5 shows how the performance
holds up at 50Msps with the DAC
generating two tones at 4.9MHz and
5.1MHz, each with a half-scale digital
100
0
–30
90
25MSPS
SFDR (dB)
–40
–50
–60
–10
SIGNAL AMPLITUDE (dBFS)
–20
0
5MSPS
SFDR = 87dB
fCLOCK = 50MSPS
fOUT = 1.002MHz
AMPL = 0dBFS
= –8.25dBm
–10
SIGNAL AMPLITUDE (dBFS)
and the doubly terminated output
gives an output level of –8.25dBm.
The SFDR of 87dB is the best in the
industry.
Figure 4 shows the single-tone
SFDR versus output frequency for a
variety of sample rates and output
frequencies. The figure shows that
SFDRs of greater than 90dB are
achievable at low frequencies. The
SFDR rolls off with output frequency
but remains better than 80dB at 5MHz
output and better than 70dB at 20MHz
output.
80
50MSPS
70
–70
60
–80
–20
–30
SFDR > 86dB
fCLOCK = 50MSPS
fOUT1 = 4.9MHz
fOUT2 = 5.09MHz
AMPL = 0dBFS
–40
–50
–60
–70
–80
–90
–90
DIGITAL AMPLITUDE = 0dBFS
50
–100
0
5
10
15
FREQUENCY (MHz)
20
25
Figure 3. Single-tone SFDR at 50Msps
Linear Technology Magazine • September 2001
0.1
1.0
10
100
fOUT (MHz)
Figure 4. SFDR vs fOUT and fCLOCK
–100
4.5
5.0
FREQUENCY (MHz)
5.5
Figure 5. 2-tone SFDR
3
0
0
95
–10
–10
90
SFDR > 74dB
fCLOCK = 50MSPS
fOUT1 = 5.02MHz
fOUT2 = 6.51MHz
fOUT3 = 11.02MHz
fOUT4 = 12.51MHz
AMPL = 0dBFS
–30
–40
–50
–60
–70
–80
–20
–40
–50
–60
–100
–100
–110
–110
0.1
4.6
8.2
11.8
15.4
FREQUENCY (MHz)
19
Figure 6. 4-tone SFDR, fCLOCK = 50Msps
80
SFDR (dB)
50
0.46
0.82
1.18
1.54
FREQUENCY (MHz)
0
1.9
–12dBFS
75
70
65
60
55
0
2
6
fOUT (MHz)
4
8
10
3
2
1
0
–1
–2
–3
sine wave amplitude (–6dBFS). By
convention, the composite signal
amplitude is called a 0dBFS signal
and the SFDR is measured relative to
either –6dBFS tone. The SFDR in a
1MHz output span is 86dB, which
includes the 3rd order intermodulation products.
Four-Tone SFDR
Moving to a four-tone measurement
in Figure 6, we have tones of 5MHz,
6.5MHz, 11MHz and 12.5MHz, each
with a quarter-scale digital sine wave
amplitude. At the same 50Msps rate
and with much more stringent conditions of higher output frequencies
and 18MHz measurement bandwidth,
the SFDR is 74dB, relative to any of
the –12dBFS tones. Taking the same
digital waveform used in Figure 6 and
reducing the clock rate by a factor of
10 (to 5Msps) we see the results of
Figure 7, where the SFDR improves to
84dB, relative to any of the –12dBFS
tones. This puts the worst spur at
96dB below the 0dB full scale of the
DAC.
7.5
10
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–5
49152
32768
16384
DIGITAL INPUT CODE
Figure 9. SFDR vs fOUT and digital amplitude
(dBFS) at fCLOCK = 25Msps
5
fOUT (MHz)
2.0
–4
50
2.5
Figure 8. SFDR vs fOUT and IOUTFS at
fCLOCK = 25Msps
DIFFERENTIAL NONLINEARITY (LSB)
–6dBFS
IOUTFS = 2.5mA
55
4
INTEGRAL NONLINEARITY (LSB)
85
IOUTFS = 5mA
70
60
5
0dBFS
90
75
65
Figure 7. 4-tone SFDR, fCLOCK = 5Msps
95
4
80
–80
–90
DIGITAL AMPLITUDE = 0dBFS
IOUTFS = 10mA
85
–70
–90
1
SFDR > 82dB
fCLOCK = 5MSPS
fOUT1 = 0.5MHz
fOUT2 = 0.65MHz
fOUT3 = 1.10MHz
fOUT4 = 1.25MHz
AMPL = 0dBFS
–30
SFDR (dB)
–20
SIGNAL AMPLITUDE (dBFS)
SIGNAL AMPLITUDE (dBFS)
DESIGN FEATURES
65535
Figure 10. Integral nonlinearity
V(IOUTA), V(IOUTB)
7FFF
8000
1mV/DIV
CLK IN
5V/DIV
5ns/DIV
Figure 12. Single-ended
midscale glitch impulse
SFDR with Reduced
Output Amplitudes
In the past, it has been common to
use a DAC as a gain control by lowering the full-scale output current of
the DAC. Figure 8 shows the SFDR
with reduced full-scale output current. As an alternative to that method,
the 16-bit resolution of the LTC1668
allows attenuation to be done in the
digital domain. Figure 9 shows the
SFDR with reduced digital sine wave
amplitude. Comparing Figures 8 and
9, we see that a 12dB reduction in the
0
32768
16384
49152
DIGITAL INPUT CODE
65535
Figure 11. Differential nonlinearity
full-scale current (2.5mA IOUTFS) gives
an 83dB SFDR at 2.5MHz but the
SFDR rolls off with increasing output
frequency. On the other hand, a 12dB
reduction in digital signal amplitude
results in an SFDR that is a little
lower at low frequencies (78dB at
2.5MHz) but it remains virtually flat
up to 10MHz, giving a much better
result than the reduced IOUTFS case.
DC and Time-Domain
Performance
Because of its good linearity, fast
settling time and low glitch, the
LTC1668 also excels in applications
requiring good DC and time-domain
performance.
1LSB DNL and 3LSB INL
The LTC1668 is a precision DAC in
addition to being fast. It uses precision bipolar transistors and laser
trimmed thin-film resistors (which
puts it in a class by itself when compared to competitors’ CMOS parts).
Figures 10 and 11 show the superior
INL and DNL for the DAC.
continued on page 17
Linear Technology Magazine • September 2001
DESIGN FEATURES
LTC1668, continued from page 4
V(IOUTA) – V(IOUTB)
V(IOUTA) – V(IOUTB)
V(IOUTA)
8000
7FFF
100mV
/DIV
1mV/DIV
FFFF
100mV
/DIV
0000
0000
FFFF
V(IOUTB)
CLK IN
5V/DIV
CLK IN
5V/DIV
CLK IN
5V/DIV
5ns/DIV
5ns/DIV
5ns/DIV
Figure 13. Differential
midscale glitch impulse
Figure 14. Single-ended output,
full-scale transition
Figure 15. LTC1688 differential
settling time
Glitch
Full-Scale Step Response
Conclusion
Figure 12 shows the single-ended
glitch impulse on both IOUTA and IOUTB.
The glitch impulse is 15pV-s on either
output and the difference is seen to
be very small. Figure 13 shows the
differential output glitch impulse
which is less than 4pV-s.
For waveform generation applications, the fast settling time of the
LTC1668 is ideal. Figure 14 shows
the full-scale settling for each output
(IOUTA and IOUTB). Figure 15 shows the
differential settling time, which is
also 18ns. Differential settling time
to 0.1% is 18ns.
The LTC1668 offers the highest level
of both AC and DC performance of
any DAC for new communications
and instrumentation applications. As
such, it should be the DAC of choice
for new designs.
LT1681/LTC1698, continued from page 11
Conclusion
100
95
EFFICIENCY (%)
36V
90
48V
72V
85
80
75
70
2
4
6
8
10 12 14
CURRENT (A)
16
18
20
Figure 6. LT1681/LTC1698 efficiency
for circuit in Figure 5
Figure 7. 48V to 3.3V/20A supply
The LT1681 and LTC1698 combine to
provide a complete solution for
synchronous forward converters.
LT1681’s current-mode operation to
250kHz combined with 72V high-side
driver reduces circuit size and complexity. The LTC1698’s built-in error
amplifier, reference and synchronous
gate driver make it the perfect solution
for isolated applications. Together,
they are the ideal choice for high
input to low voltage output DC/DC
converters.
For more information on parts featured in this issue, see
http://www.linear-tech.com/go/ltmag
Linear Technology Magazine • September 2001
17