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Experiment 13 Differential Amplifiers
Y. Shin, J.C. Rudell, W.T. Yeung, R. A. Cortina,
and R.T. Howe
UC Berkeley EE 105
1.0 Objective
In this experiment, we will examine some of the properties of both bipolar and MOS
differential gain stages. The lab begins with a procedure for setting the DC bias required
to obtain the correct operating point for a differential pair. With the bias conditions set,
you will then measure the small signal gain for both a MOS and bipolar “diff. pair”
while varying the load resistance. Two-stage differential pairs will also be examined
along with other configurations which include an emitter degenerated gain stage and
diff. pair commonly used to combat the effect of input offset voltage.
To show your understanding of the lab, your write-up should contain:
•
•
•
•
•
2-Port representations of the differential pair
A discussion on the output offset voltage.
A comparison between single-stage amplifiers and differential amplifiers
A discussion on DC biasing issues
A discussion on trade-offs between MOS and BJT differential pairs
2.0 Prelab
H & S: Chapters 11.1 - 11.2
M3501 βF = 104.3 VAn= 43.3V
N3515 VTOn = 0.88 V µnCox=79.47 µA/V2 λn = 0.06 V-1
1 of 10
Prelab
2.1 1. BJT Differential Pair
A single BJT differential pair is shown below. For RL1 and RL2=1 kΩ, calculate IBIAS to
set VO1 and VO2 at a level that will give the maximum output swing. Assume VCEsat =0.2
V and VBE = 0.7 V. With your value of IBIAS calculate the differential mode gain
Adm=vout/vin and the common mode gain Acm=vout/vin. What is the CMRR?
FIGURE 1.
Bipolar Differential Pair
Vcc=5V
RL1
RL2
vOUT
RBIAS
Q1
M3501
Q2
M3501
vin
Q3
M3501
Q4
+
_
VIC
M3501
GND
2.2 MOS Differential Pair
A single MOS differential pair is shown below. For RL1 and RL2=1kΩ, calculate IBIAS to
set VO1 and VO2 at 2.75V. Calculate the differential mode gain Adm=vout/vin and the
common mode gain Acm=vout/vin. What is the CMRR?
2 of 10
Experiment 13 - Differential Amplifiers
Procedure
FIGURE 2.
MOS Differential Pair
VDD=5V
RL1
RL2
vout
RBIAS
M1
vin
M2
W=93u W=93u
L=1.5u L=1.5u
M4
M3
W=93u
L=1.5u
W=93u
L=1.5u
+
_
VIC
GND
3.0 Procedure
3.1 BJT Differential Pair
3.1.1
DC Measurement
1. Connect up the bjt diff. pair circuit shown in figure 3. Use RL1,2=2.5kΩ and RBIAS =2
kΩ. Note the collector currents and collector voltages. Also note IBIAS.
2. Adjust Rp1 and Rp2 until VBQ1 and VBQ2 is ≅1.2V.
3. Make sure that all the transistors are in the forward active region of operation.
4. Connect a voltmeter at VO1. Adjust Rp2 and observe what happens at VO1. In particu-
lar, note the difference in the base voltages when VO1 ≅ 0 and VO1 = 5V.
5. Readjust Rp1 and Rp2 until VO1-VO2 is at a minimum (< 100mV) while making sure
that the DC values of VO1 and VO2 are approximately at 1.2V.
6. The DC voltage required at the base of Q1 and Q2 to make the differential output
voltage equal zero is referred to as the input offset voltage. By adjusting Rp1 and Rp2,
you have removed the offset voltage at the output of the circuit shown in Figure 3.
When designing any type of differential amplifier it is extremely important to minimize this offset which will be amplified if we cascade (pass the signal through a
series of gain stages) the signal through more than one amplifying stage. Now measure the input offset voltage of the circuit you have just built, Vos=VBE1-VBE2=VBQ1-
Experiment 13 - Differential Amplifiers
3 of 10
Procedure
VBQ2 using the digital multi-meter. Later in this lab we will discuss how this offset
arises and a technique to minimize the input offset voltage of a differential pair
FIGURE 3.
Bipolar Differential Pair for DC Measurements (Lab Chip 6)
PIN 28 =VCC =5V
RL1
10kΩ
RBIAS
BIAS
PIN 22
VIN1
PIN 18
VO1
RL2
PIN 19
VO2
PIN 21
VIN2
PIN 20
Q2
M3501
Q1
M3501
Rp1
Q3
M3501
10kΩ
Rp2
Q4
M3501
GND PIN 14
3.1.2
AC Measurement
1. To perform an AC analysis, modify the circuit in figure 3 to the circuit in figure 4.
Use the signal generator to apply a small sinusoidal input at vin at 10kHz. Let C1 and
C2 be large capacitors (10µF). Observe the output waveform using the oscilloscope
by connecting vo1 to Channel 1 and vo2 to Channel 2. Invert Channel 2 and add both
Channels together. What can you say about the phase of the signals at vo1 and vo2?
Why do we need the 100kΩ resistor in series with the signal source? Also, how
much is the signal attenuated between the signal source and the base of Q1? What is
Adm? What is the relationship between the differential gain and the single-ended
gain.
2. Increase the amplitude of vin until the output begins to “rail out” (clip)-record this
range of the input voltage and output voltage.
3. To measure the input resistance, measure the voltage gain vb1/vin (The gain at the
base of the resistor). Using a resistive divider relationship, find the input resistance
of the differential pair (The biasing resistors are part of the input resistance).
4. For Acm, remove RB2, RP2 and C2.and short the bases of Q1 and Q2 together. Apply a
small sinusoidal input at vin and use the oscilloscope to measure Acm by observing
the output waveform at vo1. What is CMRR for this diff. pair?
4 of 10
Experiment 13 - Differential Amplifiers
Procedure
FIGURE 4.
Bipolar Differential Pair for AC Measurements
PIN 28 =VCC =5V
RB1
10kΩ
RBIAS
100 kΩ
VO1
RL2
PIN 19
VO2
PIN 21
RL1
C1
Q1
BIAS
PIN 22
vin
M3501
VI1
PIN 18
Q2
M3501
Rp1
Q3
M3501
RB2
10kΩ
C2
VI2
PIN 20
Rp2
Q4
M3501
GND
PIN 14
4. Use SPICE to confirm your experiment. Use transistor data from previous experiments.
Note: Rp1,2 should both be about 3 kΩ.
3.2 Two Stage MOS Differential Pair
3.2.1
DC Measurements
1. A two stage diff. pair is shown in Fig. 5. Let RBIAS be 2 kΩ. Bias the gates of the first
stage (pins 5 and 6) to be 2.5V DC using a resistive divider as you did with the bipolar diff pair.
2. As before, minimize the output offset of the first stage by adjusting the variable
resistors. What is the effect of a large offset voltage on the second stage? You can
play with the variable resistors and see for yourself.
3. Again, note all the drain and bias currents. Verify that all the devices are in its saturation region.
Experiment 13 - Differential Amplifiers
5 of 10
Optional Experiments
FIGURE 5.
Two Stage MOS Differential Pair (MOSDP, Lab Chip 5)
PIN 28 =VDD=5V
3kΩ
RL1
RL2
3kΩ
2.5kΩ
2.5kΩ
RBIAS
RBIAS
VO11
PIN 20
B1AS1
PIN 16
VO12
PIN 15
M1
M2
W=93u W=93u
L=1.5u L=1.5u
VI11
PIN 12
M1
VI12
PIN 13
M4
M3
W=93u
L=1.5u
VO19
PIN 2
M2
W=93u W=93u
L=1.5u L=1.5u
M4
W=93u
L=1.5u
W=93u
L=1.5u
VO18
PIN 1
BIAS2
PIN 17
M4
W=93u
L=1.5u
GND
Note: The second stage doesn’t need to be biased. It is biased by the first stage.
3.2.2
AC Measurements
1. Repeat the procedures for the ac measurements of the bipolar diff pair. This time,
find the gain of the first stage as well as the two-stage composite amplifier.
2. As always use SPICE to verify.
4.0 Optional Experiments
4.1 Emitter Degenerated BJT Differential Pair
When trying to amplify a voltage signal, we always want to have a high input resistance.
One way of increasing the input and output impedance of a bipolar differential pair is to
degenerate the emitter of Q1 and Q2. On Lab Chip 6 there is a differential pair provided
(BJTDPDE) which will allow you to investigate some of the properties of emitter
degenerated differential pairs.
6 of 10
Experiment 13 - Differential Amplifiers
Optional Experiments
4.1.1
DC Measurements
1. Connect up the emitter degenerated diff. pair circuit shown in Figure 6. Bias the diff.
pair using the same procedure in part 3.1 of the lab. Use RL1,2=50kΩ. Adjust Rp1 and
Rp2 until VBQ1 and VBQ2 is ≅1.6V. Why is 1.6V a good bias voltage for the base of
Q1 & Q2?
2. Calculate the bias current needed for VO1 and VO2 to be equal to 2.75V. Adjust
RBIAS until the current through Q3 equals Ibias and Vo1 and Vo2 equal 2.75V.
3. Connect a voltmeter between VO1 and VO2 and adjust Rp2 until VO1 - VO2 is a mini-
mum while making sure that VO1 and VO2 are about 2.75V.
4. Now measure the offset voltage Vos=VBE1 - VBE2= VBQ1 - VBQ2. Notice that the off-
set voltage is larger than that of the non-degenerate diff. pair with the same load
resistance. (why?-explain).
4.1.2
AC Measurement
1. Apply a small sinusoidal input at vin at 10 kHz. Observe the output waveform using
the oscilloscope by connecting vo1 to Channel 1 and vo2 to Channel 2. Invert Channel 2 and add both Channels together. Measure Avd, and compare with Avd of nondegenerate case.
2. For Avc remove RB2 and RP2 and short the bases of Q1 and Q2 together. Apply a
small sinusoidal input at vin and use the oscilloscope to measure Acm by observing
the output waveform at vo1. What is CMRR for this diff. pair? Compare this with
that of the non-degenerate case. Use SPICE to calculate Avd, Avc and Rin.
FIGURE 6.
Bipolar Differential Pair with Emitter Degeneration (BJTDPDE, Lab Chip 6)
PIN 28 =VCC =5V
RB1
10kΩ
RBIAS
1ΜΩ
VO1
PIN 12
RL1
RL2
vin
RB2
10kΩ
C2
C1
Q1
BIAS
PIN 17
VO2
PIN 16
M3501
Q2
M3501
VI2
PIN 13
VI1
PIN 15
250Ω 250Ω
Rp1 (20kΩ)
Q3
M3501
Rp2(20kΩ)
Q4
M3501
GND
Experiment 13 - Differential Amplifiers
PIN 14
7 of 10
Appendix
5.0 Appendix
5.1 Offset Voltage and Device Mismatches
5.1.1 VOS of Unmatched Differential Pair
Due to a mismatch in the input transistors and in the collector load resistors, there will
be always be a slight offset in the output DC level. As explained before, this offset will
degrade the maximum output voltage swing and can potentially be amplified by cascaded gain stages. For our differential pair there isn’t much we can due to alleviate the
problem of the mismatch between load resistors. However, there is a very popular technique for lowering the mismatch between the two input transistors.
During the fabrication of integrated circuits, mismatches between identical transistors,
resistors and capacitors are created by process variations across the entire wafer. For
example, variations in the value of on-chip capacitors can be attributed to a change in
the thickness of the dielectric from one end of the wafer to the other. Process variations
can also be the result of a non-uniform implant doping or gas diffusion. The change in
process parameters across the wafer usually occur in one direction. Two adjacent
devices can still experience a significant mismatch in device parameters even though
they are physically close to each other. Fortunately, a technique know as “commoncentroid layout” exists to minimize the effect of process variations. When trying to critically match devices as in the input stage of an Operational Amplifier two devices at
adjacent angles can be combined to make one device. Figure 7 shows the basic idea of a
common-centroid, here we see two devices combined to make one large device. Any
process variation in the x or y direction will automatically be cancelled by the two
devices.
FIGURE 7.
Common Centroid Layout
Equivalent
Device 1
y
Equivalent
Device 2
Q2
Emitter
Base
Collector
Emitter
Base
Collector
Emitter
Base
Collector
Emitter
Base
Collector
Q1
Q3
Q4
x
8 of 10
Experiment 13 - Differential Amplifiers
Appendix
To exacerbate the effect of mismatch between input devices, we have deliberately laid
out a differential pair with input devices on opposite corners of Lab Chip 6 (See Figure
8). Measure the input offset voltage using the procedure in part 3.1 of this lab. Now
measure the value of the load resistors. How much of the input referred offset is attributed to the mismatch in the load resistors? How much input referred offset is due to Q1
and Q2?
FIGURE 8.
Unmatched BJT Differential Pair (BJTDPUM, Lab Chip 6)
PIN 28 =VCC=5V
10kΩ
VO1
RL2
PIN 19
VO2
PIN 21
RL1
RBIAS
VI1
PIN 18
M3501
M3501
Rp1
Q3
M3501
VI2
PIN 20
Q2
Q1
BIAS
PIN 22
10kΩ
Rp2
Q4
M3501
GND
5.1.2 VOS of Matched Differential Pair
Shown below (Figure 9) is a schematic of an on-chip differential pair with matched
input devices using a common-centroid layout. Also shown below in Figure 10, we see
the actual layout of the circuit shown in Figure 9. Try to identify and understand this
layout, as much as feasible given the black-and-white rendering. Then using the same
resistor values as you did for the unmatched diff. pair, again measure the input offset
voltage. Is there been a significant improvement in the input referred offset?
Experiment 13 - Differential Amplifiers
9 of 10
Appendix
FIGURE 9.
Circuit Diagram of Diff Pair using Common Centroid Layout (BJTDPM, Lab Chip 6)
VO2
VO1
PIN 26
PIN 23
BIAS
PIN 27
Q1
Q2
M3501
VI1
PIN 25
Q4
Q3
M3501
VI2
PIN 24
Q5
M3501
Q6
M3501
GND PIN14
FIGURE 10.
Layout of Matched Input Devices
Contact
VO1 PIN 23
Metal
VIN2 PIN 24
Q1
Q3
Q2
GND
Base
Q4
GND
r
VO2 PIN 26
VIN2 PIN 25
Collector
Q5
Q6
Emitter
BIAS PIN 27
10 of 10
Experiment 13 - Differential Amplifiers
Base
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