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LUND UNIVERSITY Dept. of Electrical and Information Technology Analog IC Design 2011 Lecture 7 – CAD tools, Simulation and layout Markus Törmänen Dept. of Electrical and Information Technology [email protected] All images are taken from Gray, Hurst, Lewis, Meyer, 5th ed., unless noted otherwise. 110919 Markus Törmänen 1 LUND UNIVERSITY Dept. of Electrical and Information Technology Contents Simulation: • Netlist • Transistor models • Process corners • Example Layout: • Design rules • Comparing layout and schematic 110919 Markus Törmänen 2 LUND UNIVERSITY Dept. of Electrical and Information Technology Simulation - Netlist Netlist and schematic • Component models Source: Johns & Martin, Analog Integrated Circuit Design 110919 Markus Törmänen 3 LUND UNIVERSITY Dept. of Electrical and Information Technology Simulation – transistor model Transistor models: • BSIM3, BSIM4 • EKV • MM9, MM11 • … Challenges: • How to model the transition between the different regions? • • • Short channel effects • • • Mobility degradation Velocity saturation Geometry dependent parameters • • Capacitances Output resistance Mobility Temperature dependence Source: B. Razavi, Design of Analog CMOS Integrated Circuits 110919 Markus Törmänen 4 LUND UNIVERSITY Dept. of Electrical and Information Technology BSIM- model Example: threshold voltage Long-channel, uniform doping: Vth = VTH0 + γ(√(Φs-Vbs) -√Φs) Non-uniform doping: Vth = VTH0 + K1(√(Φs-Vbs) -√Φs) – K2Vbs 110919 Markus Törmänen 5 LUND UNIVERSITY Dept. of Electrical and Information Technology BSIM - Summary • The model is: – Physics based - some fitting parameters Accurate Scalable – > 100 parameters – – BSIM: http://www-device.eecs.berkeley.edu/ ~bsim3/bsim4.html 110919 Markus Törmänen 6 LUND UNIVERSITY Dept. of Electrical and Information Technology Simulation – process corners • How do we take into account process variations? – – – • Lot to lot Wafer to wafer Die to die These variations are translated to speed variations – – – Typical Slow Fast Source: B. Razavi, Design of Analog CMOS Integrated Circuits 110919 Markus Törmänen 7 LUND UNIVERSITY Dept. of Electrical and Information Technology Simulation - Example Amplifier: • 2-stage Opamp 110919 Markus Törmänen 8 LUND UNIVERSITY Dept. of Electrical and Information Technology Simulation - Example Simulations: • DC, time domain, frequency domain, noise, RF, … Example: • Opamp in negative feedback configuration Av = vo/vi = 1 + 90kΩ/10kΩ = 10 110919 Markus Törmänen 9 LUND UNIVERSITY Dept. of Electrical and Information Technology Simulation - Example Non-inverting amplifier with differentiator vo/vi (s) = 1 + R1/ ZC = 1 + sCR1 110919 Markus Törmänen 10 LUND UNIVERSITY Dept. of Electrical and Information Technology Simulation - Example Open-loop opamp: Frequency response • Amplitude • Phase 110919 Markus Törmänen 11 LUND UNIVERSITY Dept. of Electrical and Information Technology Simulation - Example Amplifier in unity gain: • Step response – time domain 110919 Markus Törmänen 12 LUND UNIVERSITY Dept. of Electrical and Information Technology Simulation - Example Amplifier in unity gain, AC simulation: • Linearized circuit parameters! 110919 Markus Törmänen 13 LUND UNIVERSITY Dept. of Electrical and Information Technology Simulation - Example Noise simulation: • Noise vs frequency • Referred to input/output 110919 Markus Törmänen 14 LUND UNIVERSITY Dept. of Electrical and Information Technology 2 minute question! Discuss in groups of 2 or 3 the following questions: – What is the fundamental difference between transient and AC simulation? – Which one is more time consuming? Be prepared to give a short comment based on your group discussion… 110919 Markus Törmänen 15 LUND UNIVERSITY Dept. of Electrical and Information Technology Layout - Design rules CAD tool: • Design rule check E.g. Cadence Assura Example of design rules for a 0.13um CMOS technology: www.eit.lth.se/cadsys/umc130lnx.html ( $UMC130/docs/ ) 110919 Markus Törmänen 16 LUND UNIVERSITY Dept. of Electrical and Information Technology Layout - Comparing layout and schematic LVS: • Layout vs schematic – – – • Compare netlists Compare device sizes Compare terminals CAD tool: Assura Only after running a succesful LVS the parasitics can be extracted • Select Assura > Run RCX to do this Then, the extracted view can be used in post-layout simulations • Tool: schematic view config • • • 110919 Markus Törmänen 17 LUND UNIVERSITY Dept. of Electrical and Information Technology Links • General information on Cadence & CADtools: http://www.eit.lth.se/cadsys/cadence.html -Note that the lab manual precedes over the general information! • Simulator used in this course: Spectre 110919 Markus Törmänen 18 LUND UNIVERSITY Dept. of Electrical and Information Technology Extra - BSIM - manual 110919 Markus Törmänen 19 LUND UNIVERSITY Dept. of Electrical and Information Technology BSIM - manual 110919 Markus Törmänen 20 LUND UNIVERSITY Dept. of Electrical and Information Technology BSIM - manual 110919 Markus Törmänen 21 LUND UNIVERSITY Dept. of Electrical and Information Technology BSIM - manual 110919 Markus Törmänen 22 LUND UNIVERSITY Dept. of Electrical and Information Technology BSIM - manual 110919 Markus Törmänen 23 LUND UNIVERSITY Dept. of Electrical and Information Technology BSIM - manual 110919 Markus Törmänen 24 LUND UNIVERSITY Dept. of Electrical and Information Technology BSIM - manual 110919 Markus Törmänen 25 LUND UNIVERSITY Dept. of Electrical and Information Technology BSIM - manual 110919 Markus Törmänen 26 LUND UNIVERSITY Dept. of Electrical and Information Technology BSIM - manual 110919 Markus Törmänen 27
