COAL Notes, Week 2 Download

Transcript
Computer Organization & Assembly Language
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Week 2:
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lecture Contents
Number Conversion:Binary, octal, decimal, hexadecimal
What is x86 architecture?
X86 Architecture or 32 bit registers
Progressive list of processors
Memory segmentation model
What is x86 architecture?
x86architecture is 32 bit architecture. This architecture is being used by Intel 80836 and intel
80486 processors that is why it is referred as “x86” since their names commonly end in “86”.
The x86 architecture has 8 General-Purpose Registers (GPR), 6 Segment Registers, 1 Flags
Register and an Instruction Pointer. 64-bit x86 has additional registers.
General-Purpose Registers (GPR) - 32-bit naming conventions
The 8 GPRs are:
1.
2.
3.
4.
5.
6.
7.
8.
Accumulator register (AX). Used in arithmetic operations.
Counter register (CX). Used in shift/rotate instructions and loops.
Data register (DX). Used in arithmetic operations and I/O operations.
Base register(BX). Used as a pointer to data
Stack Pointer register (SP). Pointer to the top of the stack.
Stack Base Pointer register (BP). Used to point to the base of the stack.
Source Index register (SI). Used as a pointer to a source in stream operations.
Destination Index register (DI). Used as a pointer to a destination in stream operations.
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All registers can be accessed in 16-bit and 32-bit modes. In 16-bit mode, the register is
identified by its two-letter (AX, BX, ……) abbreviation from the list above. In 32-bit mode, this
two-letter abbreviation is prefixed with an 'E' (extended). For example, 'EAX' is the accumulator
register as a 32-bit value.
GPRs Accumulator, counter, data and base registers can be accessed in four ways as under
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32-bit
16-bit
8-bit LSB
8-bit MSB
The other four are accessed in only two ways: 32-bit and 16-bit.
Segment Registers
The 6 Segment Registers are:
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Stack Segment (SS). Pointer to the stack.
Code Segment (CS). Pointer to the code.
Data Segment (DS). Pointer to the data.
Extra Segment (ES). Pointer to extra data ('E' stands for 'Extra').
F Segment (FS). Pointer to more extra data ('F' comes after 'E').
G Segment (GS). Pointer to still more extra data ('G' comes after 'F').
EFLAGS Register
The EFLAGS is a 32-bit register used as a collection of bits representing Boolean values to store
the results of operations and the state of the processor. The detail of these bits is as follows:31 30
15 14
NT
29
13
28
12
IOPL
27
26
25
24
23
22
11
10
9
8
7
6
OF
DF
IF
TF
SF
ZF
21
20
19
18
17
16
ID
VIP
VIF
AC
VM
RF
5
4
3
2
1
0
PF
1
CF
AF
Detail of flag bits:
0.
CF : Carry Flag. Set if the last arithmetic operation produced carry or borrow
2.
PF : Parity Flag. Set if the number of set bits in the least significant byte is even.
4.
AF : Adjust Flag. Carry of 4 bit (BCD) numbers arithmetic operations.
6.
ZF : Zero Flag. Set if the result of an operation is Zero (0).
7.
SF : Sign Flag. Set if the result of an operation is negative.
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8.
TF : Trap Flag. Set if step by step debugging.
9.
IF : Interruption Flag. Set if interrupts are enabled.
10.
DF : Direction Flag. Stream direction. If set, string operations will decrement their
pointer rather than incrementing it, reading memory backwards.
11.
OF : Overflow Flag. Set if signed arithmetic operations result in a too large value
12-13. IOPL : I/O Privilege Level field (2 bits). I/O Privilege Level of the current process.
14.
NT : Nested Task flag. Controls chaining of interrupts. Set if process is nested
16.
RF : Resume Flag. Response to debug exceptions.
17.
VM : Virtual-8086 Mode. Set if in 8086 compatibility mode.
18.
AC : Alignment Check. Set if alignment checking of memory references is done.
19.
VIF : Virtual Interrupt Flag. Virtual image of IF.
20.
VIP : Virtual Interrupt Pending flag. Set if an interrupt is pending.
21.
ID : Identification Flag. Support for CPUID instruction if can be set.
Instruction Pointer
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The EIP register contains the address of the next instruction to be executed if no
branching is done.
EIP can only be read through the stack after a call instruction.the CPU executes one
instruction at a time.
Note: When referring to registers in assembly language, the names are not case-sensitive. For
example, the names EAX and eax refer to the same register.
Segmented Memory Model
Linear memory model considered whole memory like a single array of data i.e 16 bit processors
could access total memory of 216=64K that was too small for new processors. The segmented
memory system was used to expand the 64KB limit on first-generation processors.
Memory segmentation is the division of a computer's primary memory into segments or
sections. In a computer system using segmentation, a reference to a memory location includes
a value that identifies a segment and an offset within that segment. Memory is divided into
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Code Segment
Data Segment
Stack Segment
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Registers CS, DS and SS are used to store the base address of these segments respectively while
IP, SP, BP, SI, DI, and BX all can contain a 16bit offset in them.Physical address is calculated by
adding offset to segment base address i.e.
Physical address = segment base + offset address
Earlier segmentation model has no segment protection method. A process could cross
boundaries of allocated segment but current segmentation model ensure segment protection.
A process can access only that segment which has been allocated to that process.
List of Processors
 The 4-bit processors
o Intel 4004
o Intel 4040
 The 8-bit processors
o 8008
o 8080
o 8085
 The 16-bit processors:
o 8086
o 8088
o 80186
o 80188
o 80286
 32-bit processors:
o 80386
o 80486
o Original Pentium
o Pentium with MMX Technology
o Pentium Pro
o Pentium II
o Pentium III
o Celeron
o Pentium M
o Pentium D
 64-bit processors:
o Dual Core
o Core 2Duo
o Core i3
o Core i5
o Core i7
o Xeon
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